From 59641cc7fe1ee65477841dedea84efd69e71afda Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Sep 2021 13:35:36 +0100 Subject: [PATCH] add a SimRunner prepare_for_test and run_test function --- src/soc/simple/test/test_runner.py | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index a8898bf5..f8fb84e4 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -261,6 +261,16 @@ class SimRunner(StateRunner): self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en) m.submodules.simdec2 = simdec2 # pain in the neck + def prepare_for_test(self, test): + self.test = test + + def run_test(self, instructions, gen, insncode): + sim_states = yield from run_sim_state(self.dut, self.test, + self.simdec2, + instructions, gen, + insncode) + return sim_states + class HDLRunner(StateRunner): def __init__(self, dut, m, pspec): @@ -354,6 +364,9 @@ class TestRunner(FHDLTestCase): ###### PREPARATION PHASE AT START OF TEST ####### # StateRunner.prepare_for_test() + if self.run_sim: + simrun.prepare_for_test(test) + if self.run_hdl: # set up bigendian (TODO: don't do this, use MSR) yield hdlrun.issuer.core_bigendian_i.eq(bigendian) @@ -400,8 +413,7 @@ class TestRunner(FHDLTestCase): ########## if self.run_sim: - sim_states = yield from run_sim_state(self, test, - simrun.simdec2, + sim_states = yield from simrun.run_test( instructions, gen, insncode) -- 2.30.2