From 596c90d35591589e0efddda65c81609fb422a986 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 24 Mar 2020 10:28:58 +0100 Subject: [PATCH] arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] The following testcase ICEs, because these expanders will happily create a SImode 0x80000000 CONST_INT, which is not valid RTL, as CONST_INTs need to be sign extended from the mode precision to full HWI. 2020-03-24 Jakub Jelinek PR target/94286 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode instead of GEN_INT. * gcc.dg/pr94286.c: New test. --- gcc/ChangeLog | 4 ++++ gcc/config/arm/arm.md | 7 ++++--- gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/gcc.dg/pr94286.c | 11 +++++++++++ 4 files changed, 22 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr94286.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 976f87cd408..45b534b24ab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2020-03-24 Jakub Jelinek + PR target/94286 + * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode + instead of GEN_INT. + PR debug/94285 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b45109ed529..1a7ea0d701e 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1481,7 +1481,7 @@ lo_op2 = force_reg (SImode, lo_op2); if (CONST_INT_P (lo_op2)) emit_insn (gen_cmpsi2_addneg (lo_result, lo_op1, lo_op2, - GEN_INT (-INTVAL (lo_op2)))); + gen_int_mode (-INTVAL (lo_op2), SImode))); else emit_insn (gen_subsi3_compare1 (lo_result, lo_op1, lo_op2)); @@ -1525,7 +1525,8 @@ } else if (CONST_INT_P (operands[2])) emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2], - GEN_INT (-INTVAL (operands[2])))); + gen_int_mode (-INTVAL (operands[2]), + SImode))); else if (CONST_INT_P (operands[1])) { mode = CC_RSBmode; @@ -1597,7 +1598,7 @@ lo_op2 = force_reg (SImode, lo_op2); if (CONST_INT_P (lo_op2)) emit_insn (gen_cmpsi2_addneg (lo_result, lo_op1, lo_op2, - GEN_INT (-INTVAL (lo_op2)))); + gen_int_mode (-INTVAL (lo_op2), SImode))); else emit_insn (gen_subsi3_compare1 (lo_result, lo_op1, lo_op2)); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index de25dfb4f86..6747258de62 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2020-03-24 Jakub Jelinek + PR target/94286 + * gcc.dg/pr94286.c: New test. + PR debug/94285 * gfortran.dg/pr94285.f90: New test. diff --git a/gcc/testsuite/gcc.dg/pr94286.c b/gcc/testsuite/gcc.dg/pr94286.c new file mode 100644 index 00000000000..106cb751bc0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr94286.c @@ -0,0 +1,11 @@ +/* PR target/94286 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -g" } */ + +unsigned a, b; + +int +foo (void) +{ + return __builtin_sub_overflow (a, 0x80000000U, &b); +} -- 2.30.2