From 598bd6878aedc11ddffc0cc3908bfdaf86e212e8 Mon Sep 17 00:00:00 2001 From: Kelvin Nilsen Date: Wed, 4 Jan 2017 20:03:00 +0000 Subject: [PATCH] re PR target/78056 (build failure on Power7) gcc/testsuite/ChangeLog: 2017-01-04 Kelvin Nilsen PR target/78056 * gcc.target/powerpc/pr78056-1.c: New test. * gcc.target/powerpc/pr78056-2.c: New test. * gcc.target/powerpc/pr78056-3.c: New test. * gcc.target/powerpc/pr78056-4.c: New test. * gcc.target/powerpc/pr78056-5.c: New test. * gcc.target/powerpc/pr78056-6.c: New test. * gcc.target/powerpc/pr78056-7.c: New test. * gcc.target/powerpc/pr78056-8.c: New test. * lib/target-supports.exp (check_effective_target_powerpc_popcntb_ok): New procedure to test whether the effective target supports the popcntb instruction. gcc/ChangeLog: 2017-01-04 Kelvin Nilsen PR target/78056 * doc/sourcebuild.texi (PowerPC-specific attributes): Add documentation of the powerpc_popcntb_ok attribute. * config/rs6000/rs6000.c (rs6000_option_override_internal): Add code to issue warning messages if a requested CPU configuration is not supported by the binary (assembler and loader) toolchain. (spe_init_builtins): Add two assertions to prevent ICE if attempt is made to define a built-in function that has been disabled. (paired_init_builtins): Add assertion to prevent ICE if attempt is made to define a built-in function that has been disabled. (altivec_init_builtins): Add comment explaining why definition of the DST built-in functions is not preceded by an assertion check. Add assertions to prevent ICE if attempts are made to define an altivec predicate or an abs* built-in function that has been disabled. (htm_init_builtins): Add comment explaining why definition of the htm built-in functions is not preceded by an assertion check. From-SVN: r244068 --- gcc/ChangeLog | 20 +++++ gcc/config/rs6000/rs6000.c | 81 +++++++++++++++++++- gcc/doc/sourcebuild.texi | 4 + gcc/testsuite/ChangeLog | 15 ++++ gcc/testsuite/gcc.target/powerpc/pr78056-1.c | 18 +++++ gcc/testsuite/gcc.target/powerpc/pr78056-2.c | 19 +++++ gcc/testsuite/gcc.target/powerpc/pr78056-3.c | 18 +++++ gcc/testsuite/gcc.target/powerpc/pr78056-4.c | 20 +++++ gcc/testsuite/gcc.target/powerpc/pr78056-5.c | 17 ++++ gcc/testsuite/gcc.target/powerpc/pr78056-6.c | 26 +++++++ gcc/testsuite/gcc.target/powerpc/pr78056-7.c | 15 ++++ gcc/testsuite/gcc.target/powerpc/pr78056-8.c | 26 +++++++ gcc/testsuite/lib/target-supports.exp | 20 +++++ 13 files changed, 298 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-4.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-5.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-6.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-7.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr78056-8.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3a7ad9d5ffd..5568ec6c1a4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2017-01-04 Kelvin Nilsen + + PR target/78056 + * doc/sourcebuild.texi (PowerPC-specific attributes): Add + documentation of the powerpc_popcntb_ok attribute. + * config/rs6000/rs6000.c (rs6000_option_override_internal): Add + code to issue warning messages if a requested CPU configuration is + not supported by the binary (assembler and loader) toolchain. + (spe_init_builtins): Add two assertions to prevent ICE if attempt is + made to define a built-in function that has been disabled. + (paired_init_builtins): Add assertion to prevent ICE if attempt is + made to define a built-in function that has been disabled. + (altivec_init_builtins): Add comment explaining why definition + of the DST built-in functions is not preceded by an assertion + check. Add assertions to prevent ICE if attempts are made to + define an altivec predicate or an abs* built-in function that has + been disabled. + (htm_init_builtins): Add comment explaining why definition of the + htm built-in functions is not preceded by an assertion check. + 2017-01-04 Jeff Law PR tree-optimizatin/67955 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a287a2363b3..875015ce10e 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3934,6 +3934,67 @@ rs6000_option_override_internal (bool global_init_p) gcc_assert (cpu_index >= 0); + if (have_cpu) + { +#ifndef HAVE_AS_POWER9 + if (processor_target_table[rs6000_cpu_index].processor + == PROCESSOR_POWER9) + { + have_cpu = false; + warning (0, "will not generate power9 instructions because " + "assembler lacks power9 support"); + } +#endif +#ifndef HAVE_AS_POWER8 + if (processor_target_table[rs6000_cpu_index].processor + == PROCESSOR_POWER8) + { + have_cpu = false; + warning (0, "will not generate power8 instructions because " + "assembler lacks power8 support"); + } +#endif +#ifndef HAVE_AS_POPCNTD + if (processor_target_table[rs6000_cpu_index].processor + == PROCESSOR_POWER7) + { + have_cpu = false; + warning (0, "will not generate power7 instructions because " + "assembler lacks power7 support"); + } +#endif +#ifndef HAVE_AS_DFP + if (processor_target_table[rs6000_cpu_index].processor + == PROCESSOR_POWER6) + { + have_cpu = false; + warning (0, "will not generate power6 instructions because " + "assembler lacks power6 support"); + } +#endif +#ifndef HAVE_AS_POPCNTB + if (processor_target_table[rs6000_cpu_index].processor + == PROCESSOR_POWER5) + { + have_cpu = false; + warning (0, "will not generate power5 instructions because " + "assembler lacks power5 support"); + } +#endif + + if (!have_cpu) + { + /* PowerPC 64-bit LE requires at least ISA 2.07. */ + const char *default_cpu = (!TARGET_POWERPC64 + ? "powerpc" + : (BYTES_BIG_ENDIAN + ? "powerpc64" + : "powerpc64le")); + + rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu); + } + } + /* If we have a cpu, either through an explicit -mcpu= or if the compiler was configured with --with-cpu=, replace all of the ISA bits with those from the cpu, except for options that were explicitly set. If @@ -17371,6 +17432,8 @@ spe_init_builtins (void) continue; } + /* Cannot define builtin if the instruction is disabled. */ + gcc_assert (d->icode != CODE_FOR_nothing); switch (insn_data[d->icode].operand[1].mode) { case V2SImode: @@ -17401,6 +17464,8 @@ spe_init_builtins (void) continue; } + /* Cannot define builtin if the instruction is disabled. */ + gcc_assert (d->icode != CODE_FOR_nothing); switch (insn_data[d->icode].operand[1].mode) { case V2SImode: @@ -17468,6 +17533,9 @@ paired_init_builtins (void) continue; } + /* Cannot define builtin if the instruction is disabled. */ + gcc_assert (d->icode != CODE_FOR_nothing); + if (TARGET_DEBUG_BUILTIN) fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n", (int)i, get_insn_name (d->icode), (int)d->icode, @@ -17837,6 +17905,8 @@ altivec_init_builtins (void) { HOST_WIDE_INT mask = d->mask; + /* It is expected that these dst built-in functions may have + d->icode equal to CODE_FOR_nothing. */ if ((mask & builtin_mask) != mask) { if (TARGET_DEBUG_BUILTIN) @@ -17866,7 +17936,11 @@ altivec_init_builtins (void) if (rs6000_overloaded_builtin_p (d->code)) mode1 = VOIDmode; else - mode1 = insn_data[d->icode].operand[1].mode; + { + /* Cannot define builtin if the instruction is disabled. */ + gcc_assert (d->icode != CODE_FOR_nothing); + mode1 = insn_data[d->icode].operand[1].mode; + } switch (mode1) { @@ -17914,6 +17988,8 @@ altivec_init_builtins (void) continue; } + /* Cannot define builtin if the instruction is disabled. */ + gcc_assert (d->icode != CODE_FOR_nothing); mode0 = insn_data[d->icode].operand[0].mode; switch (mode0) @@ -18101,6 +18177,9 @@ htm_init_builtins (void) tree rettype; tree argtype; + /* It is expected that these htm built-in functions may have + d->icode equal to CODE_FOR_nothing. */ + if (TARGET_32BIT && TARGET_POWERPC64) gpr_type_node = long_long_unsigned_type_node; else diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 14f357a41ee..204518d38da 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1766,6 +1766,10 @@ PowerPC target supports @code{-mhtm} @item powerpc_p8vector_ok PowerPC target supports @code{-mpower8-vector} +@item powerpc_popcntb_ok +PowerPC target supports the @code{popcntb} instruction, indicating +that this target supports @code{-mcpu=power5}. + @item powerpc_ppu_ok PowerPC target supports @code{-mcpu=cell}. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0cbc8ccda8d..5a3da3ba85d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,18 @@ +2017-01-04 Kelvin Nilsen + + PR target/78056 + * gcc.target/powerpc/pr78056-1.c: New test. + * gcc.target/powerpc/pr78056-2.c: New test. + * gcc.target/powerpc/pr78056-3.c: New test. + * gcc.target/powerpc/pr78056-4.c: New test. + * gcc.target/powerpc/pr78056-5.c: New test. + * gcc.target/powerpc/pr78056-6.c: New test. + * gcc.target/powerpc/pr78056-7.c: New test. + * gcc.target/powerpc/pr78056-8.c: New test. + * lib/target-supports.exp + (check_effective_target_powerpc_popcntb_ok): New procedure to test + whether the effective target supports the popcntb instruction. + 2017-01-03 Jeff Law PR tree-optimization/67955 diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-1.c b/gcc/testsuite/gcc.target/powerpc/pr78056-1.c new file mode 100644 index 00000000000..0d37d2b08b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include + +/* Though the command line specifies power8 target, this function is + to support power9. */ +__attribute__((target("cpu=power9"))) +int get_random () +{ + return __builtin_darn_32 (); +} + +/* { dg-final { scan-assembler "darn" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-2.c b/gcc/testsuite/gcc.target/powerpc/pr78056-2.c new file mode 100644 index 00000000000..0eec2965ac0 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-2.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "" { powerpc_p9vector_ok } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include + +/* Though the command line specifies power8 target, this function is + to support power9. Expect an error message here because this target + does not support power9. */ +__attribute__((target("cpu=power9"))) +int get_random () +{ /* { dg-warning "lacks power9 support" } */ + return __builtin_darn_32 (); /* { dg-warning "implicit declaration" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-3.c b/gcc/testsuite/gcc.target/powerpc/pr78056-3.c new file mode 100644 index 00000000000..f11ef7f3b08 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power7" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include + +/* Test for the byte atomic operations on power8 using lbarx/stbcx. */ +__attribute__((target("cpu=power8"))) +char +char_fetch_add_relaxed (char *ptr, int value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +/* { dg-final { scan-assembler-times "lbarx" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-4.c b/gcc/testsuite/gcc.target/powerpc/pr78056-4.c new file mode 100644 index 00000000000..aaae13dc217 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-4.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* powerpc_vsx_ok represents power7 */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-skip-if "" { powerpc_p8vector_ok } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power7" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include + +/* Though the command line specifies power7 target, this function is + to support power8, which will fail because this platform does not + support power8. */ +__attribute__((target("cpu=power8"))) +char +char_fetch_add_relaxed (char *ptr, int value) +{ /* { dg-warning "lacks power8 support" } */ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-5.c b/gcc/testsuite/gcc.target/powerpc/pr78056-5.c new file mode 100644 index 00000000000..0454aca053c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ +/* powerpc_vsx_ok represents power7 */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power5" } */ + +/* Though the command line specifies power5 target, this function is + to support power7. */ +__attribute__((target("cpu=power7"))) +int +div_we (int a, int b) +{ + return __builtin_divwe (a, b); +} + +/* { dg-final { scan-assembler-times "divwe " 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-6.c b/gcc/testsuite/gcc.target/powerpc/pr78056-6.c new file mode 100644 index 00000000000..667aa2e2a41 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-6.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ +/* dfp_hw represents power 6 */ +/* { dg-require-effective-target dfp_hw } */ +/* powerpc_vsx_ok represents power7 */ +/* { dg-skip-if "" { powerpc_vsx_ok } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power6" } */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +#include + +/* This test follows the pattern of pr78056-2.c, which has been + * exercised with binutils 2.25. This test, however, has not + * been exercised because the author of the test does not have access + * to a development environment that succesfully bootstraps gcc + * while at the same lacking assembler support for power 7. */ + +/* Though the command line specifies power6 target, this function is + to support power7. */ +__attribute__((target("cpu=power7"))) +int +div_we (int a, int b) +{ /* { dg-warning "lacks power7 support" } */ + return __builtin_divwe (a, b); /* { dg-warning "implicit declaration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-7.c b/gcc/testsuite/gcc.target/powerpc/pr78056-7.c new file mode 100644 index 00000000000..24d91197002 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-7.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ +/* dfp_hw represents power 6 */ +/* { dg-require-effective-target dfp_hw } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power5" } */ + +/* Though the command line specifies power5 target, this function is + to support power6. */ +__attribute__((target("cpu=power6"))) +double power6 (double a, double b) +{ + return __builtin_copysign (a, b); +} +/* { dg-final { scan-assembler-times "fcpsgn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-8.c b/gcc/testsuite/gcc.target/powerpc/pr78056-8.c new file mode 100644 index 00000000000..6322e415bad --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-8.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ + +/* powerpc_popcntb_ok represents support for power 5. */ +/* { dg-require-effective-target powerpc_popcntb_ok } */ +/* dfp_hw represents support for power 6. */ +/* { dg-skip-if "" { dfp_hw } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-options "-mcpu=power5" } */ + +/* This test follows the pattern of pr78056-2.c, which has been + * exercised with binutils 2.25. This test, however, has not + * been exercised because the author of the test does not have access + * to a development environment that succesfully bootstraps gcc + * while at the same lacking assembler support for power 6. */ + +/* This test should succeed on both 32- and 64-bit configurations. */ +/* Though the command line specifies power5 target, this function is + to support power6. Expect an error message here because this target + does not support power6. */ +__attribute__((target("cpu=power6"))) +/* fabs/fnabs/fsel */ +double normal1 (double a, double b) +{ /* { dg-warning "lacks power6 support" } */ + return __builtin_copysign (a, b); /* { dg-warning "implicit declaration" } */ +} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 52744fc37ef..e4e015e7216 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2746,6 +2746,26 @@ proc check_effective_target_dfprt { } { }] } +proc check_effective_target_powerpc_popcntb_ok { } { + return [check_cached_effective_target powerpc_popcntb_ok { + + # Disable on Darwin. + if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} { + expr 0 + } else { + check_runtime_nocache powerpc_popcntb_ok { + volatile int r; + volatile int a = 0x12345678; + int main() + { + asm volatile ("popcntb %0,%1" : "=r" (r) : "r" (a)); + return 0; + } + } "-mcpu=power5" + } + }] +} + # Return 1 if the target supports executing DFP hardware instructions, # 0 otherwise. Cache the result. -- 2.30.2