From 59953367889428e2768ff07affee67d2ed2d9968 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 13 May 2020 20:23:11 +0100 Subject: [PATCH] restore field decoders (works with BE/LE) in rotator --- src/soc/shift_rot/main_stage.py | 14 +++++++++++++- src/soc/shift_rot/rotator.py | 15 ++++++++++----- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/src/soc/shift_rot/main_stage.py b/src/soc/shift_rot/main_stage.py index 0b782120..a4fdf8c4 100644 --- a/src/soc/shift_rot/main_stage.py +++ b/src/soc/shift_rot/main_stage.py @@ -31,13 +31,25 @@ class ShiftRotMainStage(PipeModBase): m = Module() comb = m.d.comb + # obtain me and mb fields from instruction. + m_fields = self.fields.instrs['M'] + md_fields = self.fields.instrs['MD'] + mb = Signal(m_fields['MB'][0:-1].shape()) + me = Signal(m_fields['ME'][0:-1].shape()) + XO = Signal(md_fields['XO'][0:-1].shape()) + comb += mb.eq(m_fields['MB'][0:-1]) + comb += me.eq(m_fields['ME'][0:-1]) + comb += XO.eq(md_fields['XO'][0:-1]) + # set up microwatt rotator module m.submodules.rotator = rotator = Rotator() comb += [ + rotator.me.eq(me), + rotator.mb.eq(mb), + rotator.XO.eq(XO), rotator.rs.eq(self.i.rs), rotator.ra.eq(self.i.ra), rotator.shift.eq(self.i.rb), - rotator.insn.eq(self.i.ctx.op.insn), rotator.is_32bit.eq(self.i.ctx.op.is_32bit), rotator.arith.eq(self.i.ctx.op.is_signed), ] diff --git a/src/soc/shift_rot/rotator.py b/src/soc/shift_rot/rotator.py index 26c4280d..035afa47 100644 --- a/src/soc/shift_rot/rotator.py +++ b/src/soc/shift_rot/rotator.py @@ -38,10 +38,13 @@ class Rotator(Elaboratable): """ def __init__(self): # input + self.me = Signal(5, reset_less=True) # ME field + self.mb = Signal(5, reset_less=True) # MB field + self.XO = Signal(1, reset_less=True) # XO field + self.ra = Signal(64, reset_less=True) # RA self.rs = Signal(64, reset_less=True) # RS self.ra = Signal(64, reset_less=True) # RA self.shift = Signal(7, reset_less=True) # RB[0:7] - self.insn = Signal(32, reset_less=True) # for mb and me fields self.is_32bit = Signal(reset_less=True) self.right_shift = Signal(reset_less=True) self.arith = Signal(reset_less=True) @@ -98,9 +101,9 @@ class Rotator(Elaboratable): # mask-begin (mb) with m.If(self.clear_left): with m.If(self.is_32bit): - comb += mb.eq(Cat(self.insn[6:11], Const(0b01, 2))) + comb += mb.eq(Cat(self.mb, Const(0b01, 2))) with m.Else(): - comb += mb.eq(Cat(self.insn[6:11], self.insn[5], Const(0b0, 1))) + comb += mb.eq(Cat(self.mb, self.XO, Const(0b0, 1))) with m.Elif(self.right_shift): # this is basically mb = sh + (is_32bit? 32: 0); with m.If(self.is_32bit): @@ -112,9 +115,11 @@ class Rotator(Elaboratable): # mask-end (me) with m.If(self.clear_right & self.is_32bit): - comb += me.eq(Cat(self.insn[1:6], Const(0b01, 2))) + # TODO: track down where this is. have to use fields. + comb += me.eq(Cat(self.me, Const(0b01, 2))) with m.Elif(self.clear_right & ~self.clear_left): - comb += me.eq(Cat(self.insn[6:11], self.insn[5], Const(0b0, 1))) + # this is me, have to use fields + comb += me.eq(Cat(self.mb, self.XO, Const(0b0, 1))) with m.Else(): # effectively, 63 - sh comb += me.eq(Cat(~self.shift[0:6], self.shift[6])) -- 2.30.2