From 59953a0d29ab7ab1dc4e293e51378c21797f5f50 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 18 Feb 2019 18:08:14 +0000 Subject: [PATCH] mul needs FPNum mantissa to be 24-bit on a and b, set 2nd arg False --- src/add/fmul.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/add/fmul.py b/src/add/fmul.py index 728074e9..29f1bade 100644 --- a/src/add/fmul.py +++ b/src/add/fmul.py @@ -20,8 +20,8 @@ class FPMUL(FPBase): m = Module() # Latches - a = FPNum(self.width) - b = FPNum(self.width) + a = FPNum(self.width, False) + b = FPNum(self.width, False) z = FPNum(self.width, False) tot = Signal(28) # sticky/round/guard bits, 23 result, 1 overflow -- 2.30.2