From 5998c101a46c5121db0fa73b3af1f180a73d7fd5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 18 Oct 2013 11:56:16 +0200
Subject: [PATCH] Added $sr, $dffsr and $dlatch cell types

---
 backends/verilog/verilog_backend.cc | 29 +--------
 kernel/celltypes.h                  |  4 +-
 techlibs/common/simlib.v            | 96 +++++++++++++++++++++++------
 3 files changed, 80 insertions(+), 49 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 5b7b601dd..e0794ad6c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -573,34 +573,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$sr")
-	{
-		RTLIL::SigSpec sig_set, sig_reset;
-
-		std::string reg_name = cellname(cell);
-		bool out_is_reg_wire = is_reg_wire(cell->connections["\\Q"], reg_name);
-
-		if (!out_is_reg_wire)
-			fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
-
-		fprintf(f, "%s" "always @*\n", indent.c_str());
-
-		fprintf(f, "%s" "    %s <= (%s | ", indent.c_str(), reg_name.c_str(), reg_name.c_str());
-		dump_cell_expr_port(f, cell, "S", false);
-		fprintf(f, ") & ~");
-		dump_cell_expr_port(f, cell, "R", false);
-		fprintf(f, ";\n");
-
-		if (!out_is_reg_wire) {
-			fprintf(f, "%s" "assign ", indent.c_str());
-			dump_sigspec(f, cell->connections["\\Q"]);
-			fprintf(f, " = %s;\n", reg_name.c_str());
-		}
-
-		return true;
-	}
-
-	// FIXME: $memrd, $memwr, $mem, $fsm
+	// FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm
 
 	return false;
 }
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 69879f39f..883ef9ee0 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -97,13 +97,15 @@ struct CellTypes
 
 	void setup_internals_mem()
 	{
+		cell_types.insert("$sr");
 		cell_types.insert("$dff");
+		cell_types.insert("$dffsr");
 		cell_types.insert("$adff");
+		cell_types.insert("$dlatch");
 		cell_types.insert("$memrd");
 		cell_types.insert("$memwr");
 		cell_types.insert("$mem");
 		cell_types.insert("$fsm");
-		cell_types.insert("$sr");
 	}
 
 	void setup_stdcells()
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 7cd9906c9..7c075b832 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -642,26 +642,6 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$sr (S, R, Q);
-
-parameter WIDTH = 0;
-
-input [WIDTH-1:0] S, R;
-output reg [WIDTH-1:0] Q;
-
-integer i;
-always @(S, R)
-	for (i = 0; i < WIDTH; i = i+1) begin
-		if (R[i])
-			Q[i] <= 0;
-		else if (S[i])
-			Q[i] <= 1;
-	end
-
-endmodule
-
-// --------------------------------------------------------
-
 module \$lut (I, O);
 
 parameter WIDTH = 0;
@@ -694,6 +674,33 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$sr (SET, CLR, Q);
+
+parameter WIDTH = 0;
+parameter SET_POLARITY = 1'b1;
+parameter CLR_POLARITY = 1'b1;
+
+input [WIDTH-1:0] SET, CLR;
+output reg [WIDTH-1:0] Q;
+
+wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
+wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
+
+genvar i;
+generate
+	for (i = 0; i < WIDTH; i = i+1) begin:bit
+		always @(posedge pos_set[i], posedge pos_clr[i])
+			if (pos_clr[i])
+				Q[i] <= 0;
+			else if (pos_set[i])
+				Q[i] <= 1;
+	end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
@@ -712,6 +719,38 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$dffsr (CLK, SET, CLR, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter SET_POLARITY = 1'b1;
+parameter CLR_POLARITY = 1'b1;
+
+input CLK;
+input [WIDTH-1:0] SET, CLR, D;
+output reg [WIDTH-1:0] Q;
+
+wire pos_clk = CLK == CLK_POLARITY;
+wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
+wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
+
+genvar i;
+generate
+	for (i = 0; i < WIDTH; i = i+1) begin:bit
+		always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
+			if (pos_clr[i])
+				Q[i] <= 0;
+			else if (pos_set[i])
+				Q[i] <= 1;
+			else
+				Q[i] <= D[i];
+	end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$adff (CLK, ARST, D, Q);
 
 parameter WIDTH = 0;
@@ -736,6 +775,23 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$dlatch (EN, D, Q);
+
+parameter WIDTH = 0;
+parameter EN_POLARITY = 1'b1;
+
+input EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+
+always @*
+	if (EN == EN_POLARITY)
+		Q <= D;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
 
 parameter NAME = "";
-- 
2.30.2