From 59afd733267d46646be8a241c7df950ee2923fe6 Mon Sep 17 00:00:00 2001
From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Tue, 28 Nov 2023 19:52:17 +0000
Subject: [PATCH] Added prefix proposal 2019 link, thx Jacob

---
 meetings/sync_up/sync_up_2023-11-28.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/meetings/sync_up/sync_up_2023-11-28.mdwn b/meetings/sync_up/sync_up_2023-11-28.mdwn
index 70bed2d9e..19eb54d79 100644
--- a/meetings/sync_up/sync_up_2023-11-28.mdwn
+++ b/meetings/sync_up/sync_up_2023-11-28.mdwn
@@ -23,6 +23,7 @@
 * Clarification of the scope of new grants.
   See [[meetings/dmitry_2023-11-24]] notes for more context.
 
+- SimpleV prefix proposal from 2019: <https://libre-soc.org/simple_v_extension/sv_prefix_proposal/>
 - RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
 - The first step is to make modifications to `svanalysis.py` to classify the RISC-V instructions.
 - Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
-- 
2.30.2