From 59b42a0df4c14288bd6bc922c187a9e218323d3d Mon Sep 17 00:00:00 2001 From: Matthew Gretton-Dann Date: Fri, 17 Sep 2010 10:42:04 +0000 Subject: [PATCH] 2010-09-17 Tejas Belagod * config/tc-arm.c (parse_psr): Add condition for matching "APSR" on non-M-arch cpus. (psrs): Add entry for PSR flags, g, nzcvq, nzcvqg. 2010-09-17 Tejas Belagod * gas/arm/msr-reg.s: New file. * gas/arm/msr-reg.d: Likewise. * gas/arm/msr-imm.s: Likewise. * gas/arm/msr-imm.d: Likewise. * gas/arm/msr-imm-bad.d: Likewise. * gas/arm/msr-imm-bad.l: Likewise. * gas/arm/msr-reg-bad.d: Likewise. * gas/arm/msr-imm-bad.d: Likewise. * gas/arm/msr-reg-thumb.d: Likewise. * gas/arm/arch7.s: Add tests for xpsr. * gas/arm/arch7.d: Likewise. --- gas/ChangeLog | 6 + gas/config/tc-arm.c | 10 +- gas/testsuite/ChangeLog | 14 +++ gas/testsuite/gas/arm/arch7.d | 2 + gas/testsuite/gas/arm/arch7.s | 2 + gas/testsuite/gas/arm/msr-imm-bad.d | 5 + gas/testsuite/gas/arm/msr-imm-bad.l | 135 +++++++++++++++++++++++ gas/testsuite/gas/arm/msr-imm.d | 141 ++++++++++++++++++++++++ gas/testsuite/gas/arm/msr-imm.s | 153 ++++++++++++++++++++++++++ gas/testsuite/gas/arm/msr-reg-bad.d | 5 + gas/testsuite/gas/arm/msr-reg-bad.l | 134 ++++++++++++++++++++++ gas/testsuite/gas/arm/msr-reg-thumb.d | 142 ++++++++++++++++++++++++ gas/testsuite/gas/arm/msr-reg.d | 141 ++++++++++++++++++++++++ gas/testsuite/gas/arm/msr-reg.s | 149 +++++++++++++++++++++++++ 14 files changed, 1038 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/arm/msr-imm-bad.d create mode 100644 gas/testsuite/gas/arm/msr-imm-bad.l create mode 100644 gas/testsuite/gas/arm/msr-imm.d create mode 100644 gas/testsuite/gas/arm/msr-imm.s create mode 100644 gas/testsuite/gas/arm/msr-reg-bad.d create mode 100644 gas/testsuite/gas/arm/msr-reg-bad.l create mode 100644 gas/testsuite/gas/arm/msr-reg-thumb.d create mode 100644 gas/testsuite/gas/arm/msr-reg.d create mode 100644 gas/testsuite/gas/arm/msr-reg.s diff --git a/gas/ChangeLog b/gas/ChangeLog index a2bac57118b..789b4362673 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2010-09-17 Tejas Belagod + + * config/tc-arm.c (parse_psr): Add condition for matching "APSR" on + non-M-arch cpus. + (psrs): Add entry for PSR flags, g, nzcvq, nzcvqg. + 2010-09-17 Tejas Belagod * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index cebf2df8138..9bba5e4949f 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -5321,7 +5321,9 @@ parse_psr (char **str) p = *str; if (strncasecmp (p, "SPSR", 4) == 0) psr_field = SPSR_BIT; - else if (strncasecmp (p, "CPSR", 4) == 0) + else if (strncasecmp (p, "CPSR", 4) == 0 + || (strncasecmp (p, "APSR", 4) == 0 + && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))) psr_field = 0; else { @@ -16214,6 +16216,8 @@ static const struct asm_psr psrs[] = {"c", PSR_c}, {"x", PSR_x}, {"s", PSR_s}, + {"g", PSR_s}, + /* Combinations of flags. */ {"fs", PSR_f | PSR_s}, {"fx", PSR_f | PSR_x}, @@ -16275,6 +16279,10 @@ static const struct asm_psr psrs[] = {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, + + /* APSR flags */ + {"nzcvq", PSR_f}, + {"nzcvqg", PSR_s | PSR_f} }; /* Table of V7M psr names. */ diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index cd5f25c72fe..971329e61c8 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2010-09-17 Tejas Belagod + + * gas/arm/msr-reg.s: New file. + * gas/arm/msr-reg.d: Likewise. + * gas/arm/msr-imm.s: Likewise. + * gas/arm/msr-imm.d: Likewise. + * gas/arm/msr-imm-bad.d: Likewise. + * gas/arm/msr-imm-bad.l: Likewise. + * gas/arm/msr-reg-bad.d: Likewise. + * gas/arm/msr-imm-bad.d: Likewise. + * gas/arm/msr-reg-thumb.d: Likewise. + * gas/arm/arch7.s: Add tests for xpsr. + * gas/arm/arch7.d: Likewise. + 2010-09-17 Tejas Belagod * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. diff --git a/gas/testsuite/gas/arm/arch7.d b/gas/testsuite/gas/arm/arch7.d index 345190bf04d..0c0b3e8273c 100644 --- a/gas/testsuite/gas/arm/arch7.d +++ b/gas/testsuite/gas/arm/arch7.d @@ -74,3 +74,5 @@ Disassembly of section .text: 0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0 0+108 <[^>]*> f380 8813 msr FAULTMASK, r0 0+10c <[^>]*> f380 8814 msr CONTROL, r0 +0+110 <[^>]*> f3ef 8003 mrs r0, PSR +0+114 <[^>]*> f380 8803 msr PSR, r0 diff --git a/gas/testsuite/gas/arm/arch7.s b/gas/testsuite/gas/arm/arch7.s index 9b30aa27cb1..4f00f5fa610 100644 --- a/gas/testsuite/gas/arm/arch7.s +++ b/gas/testsuite/gas/arm/arch7.s @@ -77,3 +77,5 @@ label2: msr basepri_max, r0 msr faultmask, r0 msr control, r0 + mrs r0, xpsr + msr xpsr, r0 diff --git a/gas/testsuite/gas/arm/msr-imm-bad.d b/gas/testsuite/gas/arm/msr-imm-bad.d new file mode 100644 index 00000000000..ae1faa7a616 --- /dev/null +++ b/gas/testsuite/gas/arm/msr-imm-bad.d @@ -0,0 +1,5 @@ +# name: Cannot use MSR with immediates in thumb mode. +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +# error-output: msr-imm-bad.l +# source: msr-imm.s +# as: -march=armv7-a -mthumb diff --git a/gas/testsuite/gas/arm/msr-imm-bad.l b/gas/testsuite/gas/arm/msr-imm-bad.l new file mode 100644 index 00000000000..4f1ef98e2c8 --- /dev/null +++ b/gas/testsuite/gas/arm/msr-imm-bad.l @@ -0,0 +1,135 @@ +[^:]*: Assembler messages: +[^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR,#0xc0000004' +[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004' +[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004' +[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004' +[^:]*:15: Error: Thumb encoding does not support an immediate here -- `msr CPSR,#0xc0000004' +[^:]*:16: Error: Thumb encoding does not support an immediate here -- `msr CPSR_s,#0xc0000004' +[^:]*:17: Error: Thumb encoding does not support an immediate here -- `msr CPSR_f,#0xc0000004' +[^:]*:18: Error: Thumb encoding does not support an immediate here -- `msr CPSR_c,#0xc0000004' +[^:]*:19: Error: Thumb encoding does not support an immediate here -- `msr CPSR_x,#0xc0000004' +[^:]*:22: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fs,#0xc0000004' +[^:]*:23: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fx,#0xc0000004' +[^:]*:24: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fc,#0xc0000004' +[^:]*:25: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sf,#0xc0000004' +[^:]*:26: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sx,#0xc0000004' +[^:]*:27: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sc,#0xc0000004' +[^:]*:28: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xf,#0xc0000004' +[^:]*:29: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xs,#0xc0000004' +[^:]*:30: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xc,#0xc0000004' +[^:]*:31: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cf,#0xc0000004' +[^:]*:32: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cs,#0xc0000004' +[^:]*:33: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cx,#0xc0000004' +[^:]*:34: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fsx,#0xc0000004' +[^:]*:35: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fsc,#0xc0000004' +[^:]*:36: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxs,#0xc0000004' +[^:]*:37: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxc,#0xc0000004' +[^:]*:38: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcs,#0xc0000004' +[^:]*:39: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcx,#0xc0000004' +[^:]*:40: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfx,#0xc0000004' +[^:]*:41: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfc,#0xc0000004' +[^:]*:42: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxf,#0xc0000004' +[^:]*:43: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxc,#0xc0000004' +[^:]*:44: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scf,#0xc0000004' +[^:]*:45: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scx,#0xc0000004' +[^:]*:46: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfs,#0xc0000004' +[^:]*:47: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfc,#0xc0000004' +[^:]*:48: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xsf,#0xc0000004' +[^:]*:49: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xsc,#0xc0000004' +[^:]*:50: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcf,#0xc0000004' +[^:]*:51: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcs,#0xc0000004' +[^:]*:52: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfs,#0xc0000004' +[^:]*:53: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfx,#0xc0000004' +[^:]*:54: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csf,#0xc0000004' +[^:]*:55: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csx,#0xc0000004' +[^:]*:56: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxf,#0xc0000004' +[^:]*:57: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxs,#0xc0000004' +[^:]*:58: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fsxc,#0xc0000004' +[^:]*:59: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fscx,#0xc0000004' +[^:]*:60: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxsc,#0xc0000004' +[^:]*:61: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxcs,#0xc0000004' +[^:]*:62: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcsx,#0xc0000004' +[^:]*:63: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcxs,#0xc0000004' +[^:]*:64: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfxc,#0xc0000004' +[^:]*:65: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfcx,#0xc0000004' +[^:]*:66: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxfc,#0xc0000004' +[^:]*:67: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxcf,#0xc0000004' +[^:]*:68: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scfx,#0xc0000004' +[^:]*:69: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scxf,#0xc0000004' +[^:]*:70: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfsc,#0xc0000004' +[^:]*:71: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfcs,#0xc0000004' +[^:]*:72: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xsfc,#0xc0000004' +[^:]*:73: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xscf,#0xc0000004' +[^:]*:74: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcfs,#0xc0000004' +[^:]*:75: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcsf,#0xc0000004' +[^:]*:76: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfsx,#0xc0000004' +[^:]*:77: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfxs,#0xc0000004' +[^:]*:78: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csfx,#0xc0000004' +[^:]*:79: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csxf,#0xc0000004' +[^:]*:80: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxfs,#0xc0000004' +[^:]*:81: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxsf,#0xc0000004' +[^:]*:85: Error: Thumb encoding does not support an immediate here -- `msr SPSR,#0xc0000004' +[^:]*:86: Error: Thumb encoding does not support an immediate here -- `msr SPSR_s,#0xc0000004' +[^:]*:87: Error: Thumb encoding does not support an immediate here -- `msr SPSR_f,#0xc0000004' +[^:]*:88: Error: Thumb encoding does not support an immediate here -- `msr SPSR_c,#0xc0000004' +[^:]*:89: Error: Thumb encoding does not support an immediate here -- `msr SPSR_x,#0xc0000004' +[^:]*:92: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fs,#0xc0000004' +[^:]*:93: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fx,#0xc0000004' +[^:]*:94: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fc,#0xc0000004' +[^:]*:95: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sf,#0xc0000004' +[^:]*:96: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sx,#0xc0000004' +[^:]*:97: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sc,#0xc0000004' +[^:]*:98: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xf,#0xc0000004' +[^:]*:99: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xs,#0xc0000004' +[^:]*:100: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xc,#0xc0000004' +[^:]*:101: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cf,#0xc0000004' +[^:]*:102: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cs,#0xc0000004' +[^:]*:103: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cx,#0xc0000004' +[^:]*:104: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fsx,#0xc0000004' +[^:]*:105: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fsc,#0xc0000004' +[^:]*:106: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxs,#0xc0000004' +[^:]*:107: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxc,#0xc0000004' +[^:]*:108: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcs,#0xc0000004' +[^:]*:109: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcx,#0xc0000004' +[^:]*:110: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfx,#0xc0000004' +[^:]*:111: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfc,#0xc0000004' +[^:]*:112: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxf,#0xc0000004' +[^:]*:113: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxc,#0xc0000004' +[^:]*:114: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scf,#0xc0000004' +[^:]*:115: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scx,#0xc0000004' +[^:]*:116: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfs,#0xc0000004' +[^:]*:117: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfc,#0xc0000004' +[^:]*:118: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xsf,#0xc0000004' +[^:]*:119: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xsc,#0xc0000004' +[^:]*:120: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcf,#0xc0000004' +[^:]*:121: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcs,#0xc0000004' +[^:]*:122: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfs,#0xc0000004' +[^:]*:123: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfx,#0xc0000004' +[^:]*:124: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csf,#0xc0000004' +[^:]*:125: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csx,#0xc0000004' +[^:]*:126: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxf,#0xc0000004' +[^:]*:127: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxs,#0xc0000004' +[^:]*:128: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fsxc,#0xc0000004' +[^:]*:129: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fscx,#0xc0000004' +[^:]*:130: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxsc,#0xc0000004' +[^:]*:131: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxcs,#0xc0000004' +[^:]*:132: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcsx,#0xc0000004' +[^:]*:133: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcxs,#0xc0000004' +[^:]*:134: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfxc,#0xc0000004' +[^:]*:135: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfcx,#0xc0000004' +[^:]*:136: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxfc,#0xc0000004' +[^:]*:137: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxcf,#0xc0000004' +[^:]*:138: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scfx,#0xc0000004' +[^:]*:139: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scxf,#0xc0000004' +[^:]*:140: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfsc,#0xc0000004' +[^:]*:141: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfcs,#0xc0000004' +[^:]*:142: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xsfc,#0xc0000004' +[^:]*:143: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xscf,#0xc0000004' +[^:]*:144: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcfs,#0xc0000004' +[^:]*:145: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcsf,#0xc0000004' +[^:]*:146: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfsx,#0xc0000004' +[^:]*:147: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfxs,#0xc0000004' +[^:]*:148: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csfx,#0xc0000004' +[^:]*:149: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csxf,#0xc0000004' +[^:]*:150: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxfs,#0xc0000004' +[^:]*:151: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxsf,#0xc0000004' diff --git a/gas/testsuite/gas/arm/msr-imm.d b/gas/testsuite/gas/arm/msr-imm.d new file mode 100644 index 00000000000..a450cb0821a --- /dev/null +++ b/gas/testsuite/gas/arm/msr-imm.d @@ -0,0 +1,141 @@ +# name: MSR immediate operands +# as: -march=armv7-a +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004 +00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004 +00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004 +0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004 +00000010 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004 +00000014 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004 +00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004 +0000001c <[^>]*> e321f113 msr CPSR_c, #-1073741820 ; 0xc0000004 +00000020 <[^>]*> e322f113 msr CPSR_x, #-1073741820 ; 0xc0000004 +00000024 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004 +00000028 <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004 +0000002c <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004 +00000030 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004 +00000034 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004 +00000038 <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004 +0000003c <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004 +00000040 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004 +00000044 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004 +00000048 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004 +0000004c <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004 +00000050 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004 +00000054 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000058 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +0000005c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000060 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +00000064 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +00000068 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +0000006c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000070 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +00000074 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000078 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +0000007c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +00000080 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +00000084 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000088 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +0000008c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000090 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +00000094 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +00000098 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +0000009c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +000000a0 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +000000a4 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +000000a8 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +000000ac <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +000000b0 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +000000b4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000b8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000bc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000c0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000c4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000c8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000cc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000d0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000d4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000d8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000dc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000e0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000e4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000e8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000ec <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000f0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000f4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000f8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000fc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000100 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000104 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000108 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +0000010c <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000110 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000114 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004 +00000118 <[^>]*> e364f113 msr SPSR_s, #-1073741820 ; 0xc0000004 +0000011c <[^>]*> e368f113 msr SPSR_f, #-1073741820 ; 0xc0000004 +00000120 <[^>]*> e361f113 msr SPSR_c, #-1073741820 ; 0xc0000004 +00000124 <[^>]*> e362f113 msr SPSR_x, #-1073741820 ; 0xc0000004 +00000128 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004 +0000012c <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004 +00000130 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004 +00000134 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004 +00000138 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004 +0000013c <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004 +00000140 <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004 +00000144 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004 +00000148 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004 +0000014c <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004 +00000150 <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004 +00000154 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004 +00000158 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +0000015c <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +00000160 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +00000164 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +00000168 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +0000016c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +00000170 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +00000174 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +00000178 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +0000017c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +00000180 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +00000184 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +00000188 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +0000018c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +00000190 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +00000194 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +00000198 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +0000019c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +000001a0 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +000001a4 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +000001a8 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +000001ac <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +000001b0 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +000001b4 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +000001b8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001bc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001c0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001c4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001c8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001cc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001d0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001d4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001d8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001dc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001e0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001e4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001e8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001ec <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001f0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001f4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001f8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001fc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000200 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000204 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000208 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +0000020c <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000210 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000214 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 diff --git a/gas/testsuite/gas/arm/msr-imm.s b/gas/testsuite/gas/arm/msr-imm.s new file mode 100644 index 00000000000..99df7f722c6 --- /dev/null +++ b/gas/testsuite/gas/arm/msr-imm.s @@ -0,0 +1,153 @@ +@ Check MSR and MRS instruction operand syntax. +@ Also check for MSR/MRS acceptance in ARM/THUMB modes. + +.section .text +.syntax unified + + @ Write to Special Register from Immediate + @ Write to application status register + msr APSR,#0xc0000004 + msr APSR_g,#0xc0000004 + msr APSR_nzcvq,#0xc0000004 + msr APSR_nzcvqg,#0xc0000004 + + @ Write to CPSR flags + msr CPSR,#0xc0000004 + msr CPSR_s,#0xc0000004 + msr CPSR_f,#0xc0000004 + msr CPSR_c,#0xc0000004 + msr CPSR_x,#0xc0000004 + + @ Write to CPSR flag combos + msr CPSR_fs, #0xc0000004 + msr CPSR_fx, #0xc0000004 + msr CPSR_fc, #0xc0000004 + msr CPSR_sf, #0xc0000004 + msr CPSR_sx, #0xc0000004 + msr CPSR_sc, #0xc0000004 + msr CPSR_xf, #0xc0000004 + msr CPSR_xs, #0xc0000004 + msr CPSR_xc, #0xc0000004 + msr CPSR_cf, #0xc0000004 + msr CPSR_cs, #0xc0000004 + msr CPSR_cx, #0xc0000004 + msr CPSR_fsx, #0xc0000004 + msr CPSR_fsc, #0xc0000004 + msr CPSR_fxs, #0xc0000004 + msr CPSR_fxc, #0xc0000004 + msr CPSR_fcs, #0xc0000004 + msr CPSR_fcx, #0xc0000004 + msr CPSR_sfx, #0xc0000004 + msr CPSR_sfc, #0xc0000004 + msr CPSR_sxf, #0xc0000004 + msr CPSR_sxc, #0xc0000004 + msr CPSR_scf, #0xc0000004 + msr CPSR_scx, #0xc0000004 + msr CPSR_xfs, #0xc0000004 + msr CPSR_xfc, #0xc0000004 + msr CPSR_xsf, #0xc0000004 + msr CPSR_xsc, #0xc0000004 + msr CPSR_xcf, #0xc0000004 + msr CPSR_xcs, #0xc0000004 + msr CPSR_cfs, #0xc0000004 + msr CPSR_cfx, #0xc0000004 + msr CPSR_csf, #0xc0000004 + msr CPSR_csx, #0xc0000004 + msr CPSR_cxf, #0xc0000004 + msr CPSR_cxs, #0xc0000004 + msr CPSR_fsxc, #0xc0000004 + msr CPSR_fscx, #0xc0000004 + msr CPSR_fxsc, #0xc0000004 + msr CPSR_fxcs, #0xc0000004 + msr CPSR_fcsx, #0xc0000004 + msr CPSR_fcxs, #0xc0000004 + msr CPSR_sfxc, #0xc0000004 + msr CPSR_sfcx, #0xc0000004 + msr CPSR_sxfc, #0xc0000004 + msr CPSR_sxcf, #0xc0000004 + msr CPSR_scfx, #0xc0000004 + msr CPSR_scxf, #0xc0000004 + msr CPSR_xfsc, #0xc0000004 + msr CPSR_xfcs, #0xc0000004 + msr CPSR_xsfc, #0xc0000004 + msr CPSR_xscf, #0xc0000004 + msr CPSR_xcfs, #0xc0000004 + msr CPSR_xcsf, #0xc0000004 + msr CPSR_cfsx, #0xc0000004 + msr CPSR_cfxs, #0xc0000004 + msr CPSR_csfx, #0xc0000004 + msr CPSR_csxf, #0xc0000004 + msr CPSR_cxfs, #0xc0000004 + msr CPSR_cxsf, #0xc0000004 + + @ Write to Saved status register + @ Write to SPSR flags + msr SPSR, #0xc0000004 + msr SPSR_s, #0xc0000004 + msr SPSR_f, #0xc0000004 + msr SPSR_c, #0xc0000004 + msr SPSR_x, #0xc0000004 + + @Write to SPSR flag combos + msr SPSR_fs, #0xc0000004 + msr SPSR_fx, #0xc0000004 + msr SPSR_fc, #0xc0000004 + msr SPSR_sf, #0xc0000004 + msr SPSR_sx, #0xc0000004 + msr SPSR_sc, #0xc0000004 + msr SPSR_xf, #0xc0000004 + msr SPSR_xs, #0xc0000004 + msr SPSR_xc, #0xc0000004 + msr SPSR_cf, #0xc0000004 + msr SPSR_cs, #0xc0000004 + msr SPSR_cx, #0xc0000004 + msr SPSR_fsx, #0xc0000004 + msr SPSR_fsc, #0xc0000004 + msr SPSR_fxs, #0xc0000004 + msr SPSR_fxc, #0xc0000004 + msr SPSR_fcs, #0xc0000004 + msr SPSR_fcx, #0xc0000004 + msr SPSR_sfx, #0xc0000004 + msr SPSR_sfc, #0xc0000004 + msr SPSR_sxf, #0xc0000004 + msr SPSR_sxc, #0xc0000004 + msr SPSR_scf, #0xc0000004 + msr SPSR_scx, #0xc0000004 + msr SPSR_xfs, #0xc0000004 + msr SPSR_xfc, #0xc0000004 + msr SPSR_xsf, #0xc0000004 + msr SPSR_xsc, #0xc0000004 + msr SPSR_xcf, #0xc0000004 + msr SPSR_xcs, #0xc0000004 + msr SPSR_cfs, #0xc0000004 + msr SPSR_cfx, #0xc0000004 + msr SPSR_csf, #0xc0000004 + msr SPSR_csx, #0xc0000004 + msr SPSR_cxf, #0xc0000004 + msr SPSR_cxs, #0xc0000004 + msr SPSR_fsxc, #0xc0000004 + msr SPSR_fscx, #0xc0000004 + msr SPSR_fxsc, #0xc0000004 + msr SPSR_fxcs, #0xc0000004 + msr SPSR_fcsx, #0xc0000004 + msr SPSR_fcxs, #0xc0000004 + msr SPSR_sfxc, #0xc0000004 + msr SPSR_sfcx, #0xc0000004 + msr SPSR_sxfc, #0xc0000004 + msr SPSR_sxcf, #0xc0000004 + msr SPSR_scfx, #0xc0000004 + msr SPSR_scxf, #0xc0000004 + msr SPSR_xfsc, #0xc0000004 + msr SPSR_xfcs, #0xc0000004 + msr SPSR_xsfc, #0xc0000004 + msr SPSR_xscf, #0xc0000004 + msr SPSR_xcfs, #0xc0000004 + msr SPSR_xcsf, #0xc0000004 + msr SPSR_cfsx, #0xc0000004 + msr SPSR_cfxs, #0xc0000004 + msr SPSR_csfx, #0xc0000004 + msr SPSR_csxf, #0xc0000004 + msr SPSR_cxfs, #0xc0000004 + msr SPSR_cxsf, #0xc0000004 + + diff --git a/gas/testsuite/gas/arm/msr-reg-bad.d b/gas/testsuite/gas/arm/msr-reg-bad.d new file mode 100644 index 00000000000..468bb61320a --- /dev/null +++ b/gas/testsuite/gas/arm/msr-reg-bad.d @@ -0,0 +1,5 @@ +# name: Cannot use flag-variant of PSR on v7m and v6m. +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +# error-output: msr-reg-bad.l +# source: msr-reg.s +# as: -march=armv7-m diff --git a/gas/testsuite/gas/arm/msr-reg-bad.l b/gas/testsuite/gas/arm/msr-reg-bad.l new file mode 100644 index 00000000000..3e97c36d394 --- /dev/null +++ b/gas/testsuite/gas/arm/msr-reg-bad.l @@ -0,0 +1,134 @@ +[^:]*: Assembler messages: +[^:]*:9: Error: syntax error -- `msr APSR_g,r9' +[^:]*:10: Error: syntax error -- `msr APSR_nzcvq,r9' +[^:]*:11: Error: syntax error -- `msr APSR_nzcvqg,r9' +[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9' +[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9' +[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9' +[^:]*:17: Error: selected processor does not support requested special purpose register -- `msr CPSR_c,r9' +[^:]*:18: Error: selected processor does not support requested special purpose register -- `msr CPSR_x,r9' +[^:]*:21: Error: selected processor does not support requested special purpose register -- `msr CPSR_fs,r9' +[^:]*:22: Error: selected processor does not support requested special purpose register -- `msr CPSR_fx,r9' +[^:]*:23: Error: selected processor does not support requested special purpose register -- `msr CPSR_fc,r9' +[^:]*:24: Error: selected processor does not support requested special purpose register -- `msr CPSR_sf,r9' +[^:]*:25: Error: selected processor does not support requested special purpose register -- `msr CPSR_sx,r9' +[^:]*:26: Error: selected processor does not support requested special purpose register -- `msr CPSR_sc,r9' +[^:]*:27: Error: selected processor does not support requested special purpose register -- `msr CPSR_xf,r9' +[^:]*:28: Error: selected processor does not support requested special purpose register -- `msr CPSR_xs,r9' +[^:]*:29: Error: selected processor does not support requested special purpose register -- `msr CPSR_xc,r9' +[^:]*:30: Error: selected processor does not support requested special purpose register -- `msr CPSR_cf,r9' +[^:]*:31: Error: selected processor does not support requested special purpose register -- `msr CPSR_cs,r9' +[^:]*:32: Error: selected processor does not support requested special purpose register -- `msr CPSR_cx,r9' +[^:]*:33: Error: selected processor does not support requested special purpose register -- `msr CPSR_fsx,r9' +[^:]*:34: Error: selected processor does not support requested special purpose register -- `msr CPSR_fsc,r9' +[^:]*:35: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxs,r9' +[^:]*:36: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxc,r9' +[^:]*:37: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcs,r9' +[^:]*:38: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcx,r9' +[^:]*:39: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfx,r9' +[^:]*:40: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfc,r9' +[^:]*:41: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxf,r9' +[^:]*:42: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxc,r9' +[^:]*:43: Error: selected processor does not support requested special purpose register -- `msr CPSR_scf,r9' +[^:]*:44: Error: selected processor does not support requested special purpose register -- `msr CPSR_scx,r9' +[^:]*:45: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfs,r9' +[^:]*:46: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfc,r9' +[^:]*:47: Error: selected processor does not support requested special purpose register -- `msr CPSR_xsf,r9' +[^:]*:48: Error: selected processor does not support requested special purpose register -- `msr CPSR_xsc,r9' +[^:]*:49: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcf,r9' +[^:]*:50: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcs,r9' +[^:]*:51: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfs,r9' +[^:]*:52: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfx,r9' +[^:]*:53: Error: selected processor does not support requested special purpose register -- `msr CPSR_csf,r9' +[^:]*:54: Error: selected processor does not support requested special purpose register -- `msr CPSR_csx,r9' +[^:]*:55: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxf,r9' +[^:]*:56: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxs,r9' +[^:]*:57: Error: selected processor does not support requested special purpose register -- `msr CPSR_fsxc,r9' +[^:]*:58: Error: selected processor does not support requested special purpose register -- `msr CPSR_fscx,r9' +[^:]*:59: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxsc,r9' +[^:]*:60: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxcs,r9' +[^:]*:61: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcsx,r9' +[^:]*:62: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcxs,r9' +[^:]*:63: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfxc,r9' +[^:]*:64: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfcx,r9' +[^:]*:65: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxfc,r9' +[^:]*:66: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxcf,r9' +[^:]*:67: Error: selected processor does not support requested special purpose register -- `msr CPSR_scfx,r9' +[^:]*:68: Error: selected processor does not support requested special purpose register -- `msr CPSR_scxf,r9' +[^:]*:69: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfsc,r9' +[^:]*:70: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfcs,r9' +[^:]*:71: Error: selected processor does not support requested special purpose register -- `msr CPSR_xsfc,r9' +[^:]*:72: Error: selected processor does not support requested special purpose register -- `msr CPSR_xscf,r9' +[^:]*:73: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcfs,r9' +[^:]*:74: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcsf,r9' +[^:]*:75: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfsx,r9' +[^:]*:76: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfxs,r9' +[^:]*:77: Error: selected processor does not support requested special purpose register -- `msr CPSR_csfx,r9' +[^:]*:78: Error: selected processor does not support requested special purpose register -- `msr CPSR_csxf,r9' +[^:]*:79: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxfs,r9' +[^:]*:80: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxsf,r9' +[^:]*:83: Error: selected processor does not support requested special purpose register -- `msr SPSR,r9' +[^:]*:84: Error: selected processor does not support requested special purpose register -- `msr SPSR_s,r9' +[^:]*:85: Error: selected processor does not support requested special purpose register -- `msr SPSR_f,r9' +[^:]*:86: Error: selected processor does not support requested special purpose register -- `msr SPSR_c,r9' +[^:]*:87: Error: selected processor does not support requested special purpose register -- `msr SPSR_x,r9' +[^:]*:90: Error: selected processor does not support requested special purpose register -- `msr SPSR_fs,r9' +[^:]*:91: Error: selected processor does not support requested special purpose register -- `msr SPSR_fx,r9' +[^:]*:92: Error: selected processor does not support requested special purpose register -- `msr SPSR_fc,r9' +[^:]*:93: Error: selected processor does not support requested special purpose register -- `msr SPSR_sf,r9' +[^:]*:94: Error: selected processor does not support requested special purpose register -- `msr SPSR_sx,r9' +[^:]*:95: Error: selected processor does not support requested special purpose register -- `msr SPSR_sc,r9' +[^:]*:96: Error: selected processor does not support requested special purpose register -- `msr SPSR_xf,r9' +[^:]*:97: Error: selected processor does not support requested special purpose register -- `msr SPSR_xs,r9' +[^:]*:98: Error: selected processor does not support requested special purpose register -- `msr SPSR_xc,r9' +[^:]*:99: Error: selected processor does not support requested special purpose register -- `msr SPSR_cf,r9' +[^:]*:100: Error: selected processor does not support requested special purpose register -- `msr SPSR_cs,r9' +[^:]*:101: Error: selected processor does not support requested special purpose register -- `msr SPSR_cx,r9' +[^:]*:102: Error: selected processor does not support requested special purpose register -- `msr SPSR_fsx,r9' +[^:]*:103: Error: selected processor does not support requested special purpose register -- `msr SPSR_fsc,r9' +[^:]*:104: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxs,r9' +[^:]*:105: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxc,r9' +[^:]*:106: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcs,r9' +[^:]*:107: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcx,r9' +[^:]*:108: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfx,r9' +[^:]*:109: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfc,r9' +[^:]*:110: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxf,r9' +[^:]*:111: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxc,r9' +[^:]*:112: Error: selected processor does not support requested special purpose register -- `msr SPSR_scf,r9' +[^:]*:113: Error: selected processor does not support requested special purpose register -- `msr SPSR_scx,r9' +[^:]*:114: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfs,r9' +[^:]*:115: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfc,r9' +[^:]*:116: Error: selected processor does not support requested special purpose register -- `msr SPSR_xsf,r9' +[^:]*:117: Error: selected processor does not support requested special purpose register -- `msr SPSR_xsc,r9' +[^:]*:118: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcf,r9' +[^:]*:119: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcs,r9' +[^:]*:120: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfs,r9' +[^:]*:121: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfx,r9' +[^:]*:122: Error: selected processor does not support requested special purpose register -- `msr SPSR_csf,r9' +[^:]*:123: Error: selected processor does not support requested special purpose register -- `msr SPSR_csx,r9' +[^:]*:124: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxf,r9' +[^:]*:125: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxs,r9' +[^:]*:126: Error: selected processor does not support requested special purpose register -- `msr SPSR_fsxc,r9' +[^:]*:127: Error: selected processor does not support requested special purpose register -- `msr SPSR_fscx,r9' +[^:]*:128: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxsc,r9' +[^:]*:129: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxcs,r9' +[^:]*:130: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcsx,r9' +[^:]*:131: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcxs,r9' +[^:]*:132: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfxc,r9' +[^:]*:133: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfcx,r9' +[^:]*:134: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxfc,r9' +[^:]*:135: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxcf,r9' +[^:]*:136: Error: selected processor does not support requested special purpose register -- `msr SPSR_scfx,r9' +[^:]*:137: Error: selected processor does not support requested special purpose register -- `msr SPSR_scxf,r9' +[^:]*:138: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfsc,r9' +[^:]*:139: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfcs,r9' +[^:]*:140: Error: selected processor does not support requested special purpose register -- `msr SPSR_xsfc,r9' +[^:]*:141: Error: selected processor does not support requested special purpose register -- `msr SPSR_xscf,r9' +[^:]*:142: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcfs,r9' +[^:]*:143: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcsf,r9' +[^:]*:144: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfsx,r9' +[^:]*:145: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfxs,r9' +[^:]*:146: Error: selected processor does not support requested special purpose register -- `msr SPSR_csfx,r9' +[^:]*:147: Error: selected processor does not support requested special purpose register -- `msr SPSR_csxf,r9' +[^:]*:148: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxfs,r9' +[^:]*:149: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxsf,r9' diff --git a/gas/testsuite/gas/arm/msr-reg-thumb.d b/gas/testsuite/gas/arm/msr-reg-thumb.d new file mode 100644 index 00000000000..0c92e567f21 --- /dev/null +++ b/gas/testsuite/gas/arm/msr-reg-thumb.d @@ -0,0 +1,142 @@ +# name: MSR register operands in thumb mode +# as: -march=armv7-a -mthumb +# source: msr-reg.s +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> f389 8900 msr CPSR_fc, r9 +00000004 <[^>]*> f389 8400 msr CPSR_s, r9 +00000008 <[^>]*> f389 8800 msr CPSR_f, r9 +0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9 +00000010 <[^>]*> f389 8900 msr CPSR_fc, r9 +00000014 <[^>]*> f389 8400 msr CPSR_s, r9 +00000018 <[^>]*> f389 8800 msr CPSR_f, r9 +0000001c <[^>]*> f389 8100 msr CPSR_c, r9 +00000020 <[^>]*> f389 8200 msr CPSR_x, r9 +00000024 <[^>]*> f389 8c00 msr CPSR_fs, r9 +00000028 <[^>]*> f389 8a00 msr CPSR_fx, r9 +0000002c <[^>]*> f389 8900 msr CPSR_fc, r9 +00000030 <[^>]*> f389 8c00 msr CPSR_fs, r9 +00000034 <[^>]*> f389 8600 msr CPSR_sx, r9 +00000038 <[^>]*> f389 8500 msr CPSR_sc, r9 +0000003c <[^>]*> f389 8a00 msr CPSR_fx, r9 +00000040 <[^>]*> f389 8600 msr CPSR_sx, r9 +00000044 <[^>]*> f389 8300 msr CPSR_xc, r9 +00000048 <[^>]*> f389 8900 msr CPSR_fc, r9 +0000004c <[^>]*> f389 8500 msr CPSR_sc, r9 +00000050 <[^>]*> f389 8300 msr CPSR_xc, r9 +00000054 <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000058 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +0000005c <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000060 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +00000064 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +00000068 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +0000006c <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000070 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +00000074 <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000078 <[^>]*> f389 8700 msr CPSR_sxc, r9 +0000007c <[^>]*> f389 8d00 msr CPSR_fsc, r9 +00000080 <[^>]*> f389 8700 msr CPSR_sxc, r9 +00000084 <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000088 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +0000008c <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000090 <[^>]*> f389 8700 msr CPSR_sxc, r9 +00000094 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +00000098 <[^>]*> f389 8700 msr CPSR_sxc, r9 +0000009c <[^>]*> f389 8d00 msr CPSR_fsc, r9 +000000a0 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +000000a4 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +000000a8 <[^>]*> f389 8700 msr CPSR_sxc, r9 +000000ac <[^>]*> f389 8b00 msr CPSR_fxc, r9 +000000b0 <[^>]*> f389 8700 msr CPSR_sxc, r9 +000000b4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000b8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000bc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000c0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000c4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000c8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000cc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000d0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000d4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000d8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000dc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000e0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000e4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000e8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000ec <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000f0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000f4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000f8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000fc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000100 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000104 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000108 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +0000010c <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000110 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000114 <[^>]*> f399 8900 msr SPSR_fc, r9 +00000118 <[^>]*> f399 8400 msr SPSR_s, r9 +0000011c <[^>]*> f399 8800 msr SPSR_f, r9 +00000120 <[^>]*> f399 8100 msr SPSR_c, r9 +00000124 <[^>]*> f399 8200 msr SPSR_x, r9 +00000128 <[^>]*> f399 8c00 msr SPSR_fs, r9 +0000012c <[^>]*> f399 8a00 msr SPSR_fx, r9 +00000130 <[^>]*> f399 8900 msr SPSR_fc, r9 +00000134 <[^>]*> f399 8c00 msr SPSR_fs, r9 +00000138 <[^>]*> f399 8600 msr SPSR_sx, r9 +0000013c <[^>]*> f399 8500 msr SPSR_sc, r9 +00000140 <[^>]*> f399 8a00 msr SPSR_fx, r9 +00000144 <[^>]*> f399 8600 msr SPSR_sx, r9 +00000148 <[^>]*> f399 8300 msr SPSR_xc, r9 +0000014c <[^>]*> f399 8900 msr SPSR_fc, r9 +00000150 <[^>]*> f399 8500 msr SPSR_sc, r9 +00000154 <[^>]*> f399 8300 msr SPSR_xc, r9 +00000158 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +0000015c <[^>]*> f399 8d00 msr SPSR_fsc, r9 +00000160 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +00000164 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +00000168 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +0000016c <[^>]*> f399 8b00 msr SPSR_fxc, r9 +00000170 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +00000174 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +00000178 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +0000017c <[^>]*> f399 8700 msr SPSR_sxc, r9 +00000180 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +00000184 <[^>]*> f399 8700 msr SPSR_sxc, r9 +00000188 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +0000018c <[^>]*> f399 8b00 msr SPSR_fxc, r9 +00000190 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +00000194 <[^>]*> f399 8700 msr SPSR_sxc, r9 +00000198 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +0000019c <[^>]*> f399 8700 msr SPSR_sxc, r9 +000001a0 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +000001a4 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +000001a8 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +000001ac <[^>]*> f399 8700 msr SPSR_sxc, r9 +000001b0 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +000001b4 <[^>]*> f399 8700 msr SPSR_sxc, r9 +000001b8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001bc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001c0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001c4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001c8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001cc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001d0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001d4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001d8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001dc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001e0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001e4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001e8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001ec <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001f0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001f4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001f8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001fc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000200 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000204 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000208 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +0000020c <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000210 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000214 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 diff --git a/gas/testsuite/gas/arm/msr-reg.d b/gas/testsuite/gas/arm/msr-reg.d new file mode 100644 index 00000000000..6531a93a3c2 --- /dev/null +++ b/gas/testsuite/gas/arm/msr-reg.d @@ -0,0 +1,141 @@ +# name: MSR register operands +# as: -march=armv7-a +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> e129f009 msr CPSR_fc, r9 +00000004 <[^>]*> e124f009 msr CPSR_s, r9 +00000008 <[^>]*> e128f009 msr CPSR_f, r9 +0000000c <[^>]*> e12cf009 msr CPSR_fs, r9 +00000010 <[^>]*> e129f009 msr CPSR_fc, r9 +00000014 <[^>]*> e124f009 msr CPSR_s, r9 +00000018 <[^>]*> e128f009 msr CPSR_f, r9 +0000001c <[^>]*> e121f009 msr CPSR_c, r9 +00000020 <[^>]*> e122f009 msr CPSR_x, r9 +00000024 <[^>]*> e12cf009 msr CPSR_fs, r9 +00000028 <[^>]*> e12af009 msr CPSR_fx, r9 +0000002c <[^>]*> e129f009 msr CPSR_fc, r9 +00000030 <[^>]*> e12cf009 msr CPSR_fs, r9 +00000034 <[^>]*> e126f009 msr CPSR_sx, r9 +00000038 <[^>]*> e125f009 msr CPSR_sc, r9 +0000003c <[^>]*> e12af009 msr CPSR_fx, r9 +00000040 <[^>]*> e126f009 msr CPSR_sx, r9 +00000044 <[^>]*> e123f009 msr CPSR_xc, r9 +00000048 <[^>]*> e129f009 msr CPSR_fc, r9 +0000004c <[^>]*> e125f009 msr CPSR_sc, r9 +00000050 <[^>]*> e123f009 msr CPSR_xc, r9 +00000054 <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000058 <[^>]*> e12df009 msr CPSR_fsc, r9 +0000005c <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000060 <[^>]*> e12bf009 msr CPSR_fxc, r9 +00000064 <[^>]*> e12df009 msr CPSR_fsc, r9 +00000068 <[^>]*> e12bf009 msr CPSR_fxc, r9 +0000006c <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000070 <[^>]*> e12df009 msr CPSR_fsc, r9 +00000074 <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000078 <[^>]*> e127f009 msr CPSR_sxc, r9 +0000007c <[^>]*> e12df009 msr CPSR_fsc, r9 +00000080 <[^>]*> e127f009 msr CPSR_sxc, r9 +00000084 <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000088 <[^>]*> e12bf009 msr CPSR_fxc, r9 +0000008c <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000090 <[^>]*> e127f009 msr CPSR_sxc, r9 +00000094 <[^>]*> e12bf009 msr CPSR_fxc, r9 +00000098 <[^>]*> e127f009 msr CPSR_sxc, r9 +0000009c <[^>]*> e12df009 msr CPSR_fsc, r9 +000000a0 <[^>]*> e12bf009 msr CPSR_fxc, r9 +000000a4 <[^>]*> e12df009 msr CPSR_fsc, r9 +000000a8 <[^>]*> e127f009 msr CPSR_sxc, r9 +000000ac <[^>]*> e12bf009 msr CPSR_fxc, r9 +000000b0 <[^>]*> e127f009 msr CPSR_sxc, r9 +000000b4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000b8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000bc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000c0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000c4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000c8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000cc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000d0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000d4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000d8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000dc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000e0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000e4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000e8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000ec <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000f0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000f4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000f8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000fc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000100 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000104 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000108 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +0000010c <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000110 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000114 <[^>]*> e169f009 msr SPSR_fc, r9 +00000118 <[^>]*> e164f009 msr SPSR_s, r9 +0000011c <[^>]*> e168f009 msr SPSR_f, r9 +00000120 <[^>]*> e161f009 msr SPSR_c, r9 +00000124 <[^>]*> e162f009 msr SPSR_x, r9 +00000128 <[^>]*> e16cf009 msr SPSR_fs, r9 +0000012c <[^>]*> e16af009 msr SPSR_fx, r9 +00000130 <[^>]*> e169f009 msr SPSR_fc, r9 +00000134 <[^>]*> e16cf009 msr SPSR_fs, r9 +00000138 <[^>]*> e166f009 msr SPSR_sx, r9 +0000013c <[^>]*> e165f009 msr SPSR_sc, r9 +00000140 <[^>]*> e16af009 msr SPSR_fx, r9 +00000144 <[^>]*> e166f009 msr SPSR_sx, r9 +00000148 <[^>]*> e163f009 msr SPSR_xc, r9 +0000014c <[^>]*> e169f009 msr SPSR_fc, r9 +00000150 <[^>]*> e165f009 msr SPSR_sc, r9 +00000154 <[^>]*> e163f009 msr SPSR_xc, r9 +00000158 <[^>]*> e16ef009 msr SPSR_fsx, r9 +0000015c <[^>]*> e16df009 msr SPSR_fsc, r9 +00000160 <[^>]*> e16ef009 msr SPSR_fsx, r9 +00000164 <[^>]*> e16bf009 msr SPSR_fxc, r9 +00000168 <[^>]*> e16df009 msr SPSR_fsc, r9 +0000016c <[^>]*> e16bf009 msr SPSR_fxc, r9 +00000170 <[^>]*> e16ef009 msr SPSR_fsx, r9 +00000174 <[^>]*> e16df009 msr SPSR_fsc, r9 +00000178 <[^>]*> e16ef009 msr SPSR_fsx, r9 +0000017c <[^>]*> e167f009 msr SPSR_sxc, r9 +00000180 <[^>]*> e16df009 msr SPSR_fsc, r9 +00000184 <[^>]*> e167f009 msr SPSR_sxc, r9 +00000188 <[^>]*> e16ef009 msr SPSR_fsx, r9 +0000018c <[^>]*> e16bf009 msr SPSR_fxc, r9 +00000190 <[^>]*> e16ef009 msr SPSR_fsx, r9 +00000194 <[^>]*> e167f009 msr SPSR_sxc, r9 +00000198 <[^>]*> e16bf009 msr SPSR_fxc, r9 +0000019c <[^>]*> e167f009 msr SPSR_sxc, r9 +000001a0 <[^>]*> e16df009 msr SPSR_fsc, r9 +000001a4 <[^>]*> e16bf009 msr SPSR_fxc, r9 +000001a8 <[^>]*> e16df009 msr SPSR_fsc, r9 +000001ac <[^>]*> e167f009 msr SPSR_sxc, r9 +000001b0 <[^>]*> e16bf009 msr SPSR_fxc, r9 +000001b4 <[^>]*> e167f009 msr SPSR_sxc, r9 +000001b8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001bc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001c0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001c4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001c8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001cc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001d0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001d4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001d8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001dc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001e0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001e4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001e8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001ec <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001f0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001f4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001f8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001fc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000200 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000204 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000208 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +0000020c <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000210 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000214 <[^>]*> e16ff009 msr SPSR_fsxc, r9 diff --git a/gas/testsuite/gas/arm/msr-reg.s b/gas/testsuite/gas/arm/msr-reg.s new file mode 100644 index 00000000000..beb22b6f3d1 --- /dev/null +++ b/gas/testsuite/gas/arm/msr-reg.s @@ -0,0 +1,149 @@ +@ Check MSR and MRS instruction operand syntax. +@ Also check for MSR/MRS acceptance in ARM/THUMB modes. + +.section .text +.syntax unified + + @ Write to Special Register from register + msr APSR,r9 + msr APSR_g,r9 + msr APSR_nzcvq,r9 + msr APSR_nzcvqg,r9 + + @ Write to CPSR flags + msr CPSR,r9 + msr CPSR_s,r9 + msr CPSR_f,r9 + msr CPSR_c,r9 + msr CPSR_x,r9 + + @ Write to CPSR flag combos + msr CPSR_fs, r9 + msr CPSR_fx, r9 + msr CPSR_fc, r9 + msr CPSR_sf, r9 + msr CPSR_sx, r9 + msr CPSR_sc, r9 + msr CPSR_xf, r9 + msr CPSR_xs, r9 + msr CPSR_xc, r9 + msr CPSR_cf, r9 + msr CPSR_cs, r9 + msr CPSR_cx, r9 + msr CPSR_fsx, r9 + msr CPSR_fsc, r9 + msr CPSR_fxs, r9 + msr CPSR_fxc, r9 + msr CPSR_fcs, r9 + msr CPSR_fcx, r9 + msr CPSR_sfx, r9 + msr CPSR_sfc, r9 + msr CPSR_sxf, r9 + msr CPSR_sxc, r9 + msr CPSR_scf, r9 + msr CPSR_scx, r9 + msr CPSR_xfs, r9 + msr CPSR_xfc, r9 + msr CPSR_xsf, r9 + msr CPSR_xsc, r9 + msr CPSR_xcf, r9 + msr CPSR_xcs, r9 + msr CPSR_cfs, r9 + msr CPSR_cfx, r9 + msr CPSR_csf, r9 + msr CPSR_csx, r9 + msr CPSR_cxf, r9 + msr CPSR_cxs, r9 + msr CPSR_fsxc, r9 + msr CPSR_fscx, r9 + msr CPSR_fxsc, r9 + msr CPSR_fxcs, r9 + msr CPSR_fcsx, r9 + msr CPSR_fcxs, r9 + msr CPSR_sfxc, r9 + msr CPSR_sfcx, r9 + msr CPSR_sxfc, r9 + msr CPSR_sxcf, r9 + msr CPSR_scfx, r9 + msr CPSR_scxf, r9 + msr CPSR_xfsc, r9 + msr CPSR_xfcs, r9 + msr CPSR_xsfc, r9 + msr CPSR_xscf, r9 + msr CPSR_xcfs, r9 + msr CPSR_xcsf, r9 + msr CPSR_cfsx, r9 + msr CPSR_cfxs, r9 + msr CPSR_csfx, r9 + msr CPSR_csxf, r9 + msr CPSR_cxfs, r9 + msr CPSR_cxsf, r9 + + @ Write to SPSR flags + msr SPSR,r9 + msr SPSR_s,r9 + msr SPSR_f,r9 + msr SPSR_c,r9 + msr SPSR_x,r9 + + @ Write to Saved status register + msr SPSR_fs, r9 + msr SPSR_fx, r9 + msr SPSR_fc, r9 + msr SPSR_sf, r9 + msr SPSR_sx, r9 + msr SPSR_sc, r9 + msr SPSR_xf, r9 + msr SPSR_xs, r9 + msr SPSR_xc, r9 + msr SPSR_cf, r9 + msr SPSR_cs, r9 + msr SPSR_cx, r9 + msr SPSR_fsx, r9 + msr SPSR_fsc, r9 + msr SPSR_fxs, r9 + msr SPSR_fxc, r9 + msr SPSR_fcs, r9 + msr SPSR_fcx, r9 + msr SPSR_sfx, r9 + msr SPSR_sfc, r9 + msr SPSR_sxf, r9 + msr SPSR_sxc, r9 + msr SPSR_scf, r9 + msr SPSR_scx, r9 + msr SPSR_xfs, r9 + msr SPSR_xfc, r9 + msr SPSR_xsf, r9 + msr SPSR_xsc, r9 + msr SPSR_xcf, r9 + msr SPSR_xcs, r9 + msr SPSR_cfs, r9 + msr SPSR_cfx, r9 + msr SPSR_csf, r9 + msr SPSR_csx, r9 + msr SPSR_cxf, r9 + msr SPSR_cxs, r9 + msr SPSR_fsxc, r9 + msr SPSR_fscx, r9 + msr SPSR_fxsc, r9 + msr SPSR_fxcs, r9 + msr SPSR_fcsx, r9 + msr SPSR_fcxs, r9 + msr SPSR_sfxc, r9 + msr SPSR_sfcx, r9 + msr SPSR_sxfc, r9 + msr SPSR_sxcf, r9 + msr SPSR_scfx, r9 + msr SPSR_scxf, r9 + msr SPSR_xfsc, r9 + msr SPSR_xfcs, r9 + msr SPSR_xsfc, r9 + msr SPSR_xscf, r9 + msr SPSR_xcfs, r9 + msr SPSR_xcsf, r9 + msr SPSR_cfsx, r9 + msr SPSR_cfxs, r9 + msr SPSR_csfx, r9 + msr SPSR_csxf, r9 + msr SPSR_cxfs, r9 + msr SPSR_cxsf, r9 -- 2.30.2