From 59bbbeb50b419c53121a53a96b5b003f276b626d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 25 May 2020 16:24:50 +0100 Subject: [PATCH] yield blank so test passes --- src/soc/experiment/compalu_multi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 7c9b8b07..d95389cf 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -414,11 +414,11 @@ class CompUnitParallelTest: def rd(self, rd_idx): # monitor self.dut.rd.req[rd_idx] and sets dut.rd.go[idx] for one cycle - pass + yield def wr(self, wr_idx): # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle - pass + yield def test_compunit_regspec1(): from alu_hier import ALU -- 2.30.2