From 59c92f760e95933407d1db1c086237ca39592b82 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Sun, 17 Jun 2007 13:06:02 +0000 Subject: [PATCH] m68k.h (ISA_HAS_FF1, [...]): New. * config/m68k/m68k.h (ISA_HAS_FF1, ISA_HAS_MVS_MVZ): New. * config/m68k/m68k.md: Use ISA_HAS_FF1 and ISA_HAS_MVS_MVZ as appropriate. From-SVN: r125772 --- gcc/ChangeLog | 6 ++++++ gcc/config/m68k/m68k.h | 4 ++++ gcc/config/m68k/m68k.md | 26 +++++++++++++------------- 3 files changed, 23 insertions(+), 13 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 30406dd62de..21cdb03c5c2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2007-06-17 Nathan Sidwell + + * config/m68k/m68k.h (ISA_HAS_FF1, ISA_HAS_MVS_MVZ): New. + * config/m68k/m68k.md: Use ISA_HAS_FF1 and ISA_HAS_MVS_MVZ as + appropriate. + 2007-06-17 Eric Botcazou * config/sparc/sparc.c (sparc_vis_init_builtins): Retrieve the diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 6591380b2d2..e84994b7f10 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -245,6 +245,10 @@ Boston, MA 02110-1301, USA. */ #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) +/* Some instructions are common to more than one ISA. */ +#define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC) +#define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC) + #define TUNE_68000 (m68k_tune == u68000) #define TUNE_68010 (m68k_tune == u68010) #define TUNE_68000_10 (TUNE_68000 || TUNE_68010) diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 19abe624c29..5095398f158 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -1391,7 +1391,7 @@ (define_insn "*zero_extendhisi2_cf" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] - "TARGET_ISAB" + "ISA_HAS_MVS_MVZ" "mvz%.w %1,%0") (define_insn "zero_extendhisi2" @@ -1415,7 +1415,7 @@ (define_insn "*zero_extendqisi2_cfv4" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] - "TARGET_ISAB" + "ISA_HAS_MVS_MVZ" "mvz%.b %1,%0") (define_insn "zero_extendqisi2" @@ -1429,7 +1429,7 @@ (define_split [(set (match_operand 0 "register_operand" "") (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))] - "!TARGET_ISAB + "!ISA_HAS_MVS_MVZ && reload_completed && reg_mentioned_p (operands[0], operands[1])" [(set (strict_low_part (match_dup 2)) @@ -1445,7 +1445,7 @@ (define_split [(set (match_operand 0 "register_operand" "") (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))] - "!TARGET_ISAB && reload_completed" + "!ISA_HAS_MVS_MVZ && reload_completed" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) @@ -1463,7 +1463,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_ISAB) + if (ISA_HAS_MVS_MVZ) return "mvs%.b %1,%2\;smi %0\;extb%.l %0"; if (TARGET_68020 || TARGET_COLDFIRE) { @@ -1489,7 +1489,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_ISAB) + if (ISA_HAS_MVS_MVZ) return "mvs%.w %1,%2\;smi %0\;extb%.l %0"; if (TARGET_68020 || TARGET_COLDFIRE) return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0"; @@ -1567,14 +1567,14 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (sign_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] - "TARGET_ISAB" + "ISA_HAS_MVS_MVZ" "mvs%.w %1,%0") (define_insn "*68k_extendhisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a") (sign_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))] - "!TARGET_ISAB" + "!ISA_HAS_MVS_MVZ" { if (ADDRESS_REG_P (operands[0])) return "move%.w %1,%0"; @@ -1596,13 +1596,13 @@ (define_insn "*cfv4_extendqisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))] - "TARGET_ISAB" + "ISA_HAS_MVS_MVZ" "mvs%.b %1,%0") (define_insn "*68k_extendqisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] - "TARGET_68020 || (TARGET_COLDFIRE && !TARGET_ISAB)" + "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)" "extb%.l %0") ;; Conversions between float and double. @@ -3114,7 +3114,7 @@ (umod:HI (match_dup 1) (match_dup 2)))] "!TARGET_COLDFIRE || TARGET_CF_HWDIV" { - if (TARGET_ISAB) + if (ISA_HAS_MVS_MVZ) output_asm_insn (MOTOROLA ? "mvz%.w %0,%0\;divu%.w %2,%0" : "mvz%.w %0,%0\;divu %2,%0", @@ -3238,7 +3238,7 @@ (match_operand:SI 2 "general_src_operand" "d,dmsK")))] "TARGET_COLDFIRE" { - if (TARGET_ISAB + if (ISA_HAS_MVS_MVZ && DATA_REG_P (operands[0]) && GET_CODE (operands[2]) == CONST_INT) { @@ -4005,7 +4005,7 @@ (define_insn "clzsi2" [(set (match_operand:SI 0 "register_operand" "=d") (clz:SI (match_operand:SI 1 "register_operand" "0")))] - "TARGET_ISAAPLUS || TARGET_ISAC" + "ISA_HAS_FF1" "ff1 %0") ;; one complement instructions -- 2.30.2