From 59f44fab888b7d7bb2f57cca5af845e7656f6f9c Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Thu, 7 Jun 2018 11:55:23 +0530 Subject: [PATCH] arch-power: Add fields for VA form instructions This introduces the extended opcode field and the operand field RC for VA form instructions. Change-Id: I60d1bff6e7c7dd41e6fbe28a5f012b6fd66e7bc3 Signed-off-by: Sandipan Das --- src/arch/power/isa/bitfields.isa | 2 ++ src/arch/power/isa/operands.isa | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa index fc4e867f4..44fc3c3ab 100644 --- a/src/arch/power/isa/bitfields.isa +++ b/src/arch/power/isa/bitfields.isa @@ -38,6 +38,7 @@ def bitfield PO <31:26>; def bitfield A_XO <5:1>; def bitfield DS_XO <1:0>; def bitfield DX_XO <5:1>; +def bitfield VA_XO <5:0>; def bitfield X_XO <10:1>; def bitfield XFL_XO <10:1>; def bitfield XFX_XO <10:1>; @@ -47,6 +48,7 @@ def bitfield XO_XO <9:1>; // Register fields def bitfield RA <20:16>; def bitfield RB <15:11>; +def bitfield RC <10:6>; def bitfield RS <25:21>; def bitfield RT <25:21>; def bitfield FRA <20:16>; diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index 6cc72fe04..db440805e 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -44,7 +44,8 @@ def operands {{ 'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1), 'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2), 'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3), - 'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4), + 'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4), + 'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5), # General Purpose Floating Point Reg Operands 'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1), -- 2.30.2