From 59fa71593d4b1966850c9313e4017bdabf010302 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 5 Jul 2018 16:51:40 +0200 Subject: [PATCH] core/cpu/vexriscv/core: improve indentation --- litex/soc/cores/cpu/vexriscv/core.py | 62 ++++++++++++++-------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 81a51536..0f905b90 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -171,37 +171,37 @@ class VexRiscv(Module, AutoCSR): self.comb += self.debug_reset.eq(0) self.specials += Instance("VexRiscv", - i_clk=ClockSignal(), - i_reset=i_reset, - - i_externalResetVector=cpu_reset_address, - i_externalInterruptArray=self.interrupt, - i_timerInterrupt=0, - - o_iBusWishbone_ADR=i.adr, - o_iBusWishbone_DAT_MOSI=i.dat_w, - o_iBusWishbone_SEL=i.sel, - o_iBusWishbone_CYC=i.cyc, - o_iBusWishbone_STB=i.stb, - o_iBusWishbone_WE=i.we, - o_iBusWishbone_CTI=i.cti, - o_iBusWishbone_BTE=i.bte, - i_iBusWishbone_DAT_MISO=i.dat_r, - i_iBusWishbone_ACK=i.ack, - i_iBusWishbone_ERR=i.err, - - o_dBusWishbone_ADR=d.adr, - o_dBusWishbone_DAT_MOSI=d.dat_w, - o_dBusWishbone_SEL=d.sel, - o_dBusWishbone_CYC=d.cyc, - o_dBusWishbone_STB=d.stb, - o_dBusWishbone_WE=d.we, - o_dBusWishbone_CTI=d.cti, - o_dBusWishbone_BTE=d.bte, - i_dBusWishbone_DAT_MISO=d.dat_r, - i_dBusWishbone_ACK=d.ack, - i_dBusWishbone_ERR=d.err, - **kwargs) + i_clk=ClockSignal(), + i_reset=i_reset, + + i_externalResetVector=cpu_reset_address, + i_externalInterruptArray=self.interrupt, + i_timerInterrupt=0, + + o_iBusWishbone_ADR=i.adr, + o_iBusWishbone_DAT_MOSI=i.dat_w, + o_iBusWishbone_SEL=i.sel, + o_iBusWishbone_CYC=i.cyc, + o_iBusWishbone_STB=i.stb, + o_iBusWishbone_WE=i.we, + o_iBusWishbone_CTI=i.cti, + o_iBusWishbone_BTE=i.bte, + i_iBusWishbone_DAT_MISO=i.dat_r, + i_iBusWishbone_ACK=i.ack, + i_iBusWishbone_ERR=i.err, + + o_dBusWishbone_ADR=d.adr, + o_dBusWishbone_DAT_MOSI=d.dat_w, + o_dBusWishbone_SEL=d.sel, + o_dBusWishbone_CYC=d.cyc, + o_dBusWishbone_STB=d.stb, + o_dBusWishbone_WE=d.we, + o_dBusWishbone_CTI=d.cti, + o_dBusWishbone_BTE=d.bte, + i_dBusWishbone_DAT_MISO=d.dat_r, + i_dBusWishbone_ACK=d.ack, + i_dBusWishbone_ERR=d.err, + **kwargs) # add verilog sources self.add_sources(platform, source_file) -- 2.30.2