From 5a08f711bad41ae07a2df59ad8205d7440b1765c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Apr 2019 14:55:02 +0100
Subject: [PATCH] replace i_ready with ready_i and o_valid with valid_o

---
 src/add/fpadd/statemachine.py    |   8 +--
 src/add/fpbase.py                |   6 +-
 src/add/fpcommon/putz.py         |  14 ++--
 src/add/multipipe.py             |  26 +++----
 src/add/queue.py                 |  14 ++--
 src/add/singlepipe.py            | 104 +++++++++++++--------------
 src/add/test_buf_pipe.py         | 120 +++++++++++++++----------------
 src/add/test_fpadd_pipe.py       |   8 +--
 src/add/test_fsm_experiment.py   |   4 +-
 src/add/test_inout_mux_pipe.py   |   8 +--
 src/add/test_outmux_pipe.py      |  10 +--
 src/add/test_prioritymux_pipe.py |   8 +--
 src/add/unit_test_single.py      |  12 ++--
 13 files changed, 171 insertions(+), 171 deletions(-)

diff --git a/src/add/fpadd/statemachine.py b/src/add/fpadd/statemachine.py
index 1ece16d8..94b52869 100644
--- a/src/add/fpadd/statemachine.py
+++ b/src/add/fpadd/statemachine.py
@@ -206,13 +206,13 @@ class FPADDBase(FPState):
                      self.in_t.ack.eq(self.mod.in_t.ack),
                      self.o.mid.eq(self.mod.o.mid),
                      self.o.z.v.eq(self.mod.o.z.v),
-                     self.o.z.o_valid.eq(self.mod.o.z.o_valid),
-                     self.mod.o.z.i_ready.eq(self.o.z.i_ready_test),
+                     self.o.z.valid_o.eq(self.mod.o.z.valid_o),
+                     self.mod.o.z.ready_i.eq(self.o.z.ready_i_test),
                     ]
 
         m.d.sync += self.add_stb.eq(add_stb)
         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
-        m.d.sync += self.o.z.i_ready.eq(0) # likewise
+        m.d.sync += self.o.z.ready_i.eq(0) # likewise
         #m.d.sync += self.in_t.stb.eq(0)
 
         m.submodules.fpadd = self.mod
@@ -234,7 +234,7 @@ class FPADDBase(FPState):
             with m.Else():
                 m.d.sync += [self.add_ack.eq(0),
                              self.in_t.stb.eq(0),
-                             self.o.z.i_ready.eq(1),
+                             self.o.z.ready_i.eq(1),
                             ]
         with m.Else():
             # done: acknowledge, and write out id and value
diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 56b04a2f..35197608 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -690,11 +690,11 @@ class FPBase:
         m.d.sync += [
           out_z.v.eq(z.v)
         ]
-        with m.If(out_z.o_valid & out_z.i_ready_test):
-            m.d.sync += out_z.o_valid.eq(0)
+        with m.If(out_z.valid_o & out_z.ready_i_test):
+            m.d.sync += out_z.valid_o.eq(0)
             m.next = next_state
         with m.Else():
-            m.d.sync += out_z.o_valid.eq(1)
+            m.d.sync += out_z.valid_o.eq(1)
 
 
 class FPState(FPBase):
diff --git a/src/add/fpcommon/putz.py b/src/add/fpcommon/putz.py
index 6b619ccb..8173ed85 100644
--- a/src/add/fpcommon/putz.py
+++ b/src/add/fpcommon/putz.py
@@ -25,11 +25,11 @@ class FPPutZ(FPState):
         m.d.sync += [
           self.out_z.z.v.eq(self.in_z)
         ]
-        with m.If(self.out_z.z.o_valid & self.out_z.z.i_ready_test):
-            m.d.sync += self.out_z.z.o_valid.eq(0)
+        with m.If(self.out_z.z.valid_o & self.out_z.z.ready_i_test):
+            m.d.sync += self.out_z.z.valid_o.eq(0)
             m.next = self.to_state
         with m.Else():
-            m.d.sync += self.out_z.z.o_valid.eq(1)
+            m.d.sync += self.out_z.z.valid_o.eq(1)
 
 
 class FPPutZIdx(FPState):
@@ -46,15 +46,15 @@ class FPPutZIdx(FPState):
     def action(self, m):
         outz_stb = Signal(reset_less=True)
         outz_ack = Signal(reset_less=True)
-        m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].o_valid),
-                     outz_ack.eq(self.out_zs[self.in_mid].i_ready_test),
+        m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].valid_o),
+                     outz_ack.eq(self.out_zs[self.in_mid].ready_i_test),
                     ]
         m.d.sync += [
           self.out_zs[self.in_mid].v.eq(self.in_z.v)
         ]
         with m.If(outz_stb & outz_ack):
-            m.d.sync += self.out_zs[self.in_mid].o_valid.eq(0)
+            m.d.sync += self.out_zs[self.in_mid].valid_o.eq(0)
             m.next = self.to_state
         with m.Else():
-            m.d.sync += self.out_zs[self.in_mid].o_valid.eq(1)
+            m.d.sync += self.out_zs[self.in_mid].valid_o.eq(1)
 
diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index 14c01bed..d679f7b2 100644
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -189,11 +189,11 @@ class CombMultiOutPipeline(MultiOutControlBase):
         # all outputs to next stages first initialised to zero (invalid)
         # the only output "active" is then selected by the muxid
         for i in range(len(self.n)):
-            m.d.comb += self.n[i].o_valid.eq(0)
-        data_valid = self.n[mid].o_valid
-        m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].i_ready)
+            m.d.comb += self.n[i].valid_o.eq(0)
+        data_valid = self.n[mid].valid_o
+        m.d.comb += self.p.ready_o.eq(~data_valid | self.n[mid].ready_i)
         m.d.comb += data_valid.eq(p_valid_i | \
-                                    (~self.n[mid].i_ready & data_valid))
+                                    (~self.n[mid].ready_i & data_valid))
         with m.If(pv):
             m.d.comb += eq(r_data, self.p.i_data)
         m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))
@@ -235,41 +235,41 @@ class CombMultiInPipeline(MultiInControlBase):
         r_data = []
         data_valid = []
         p_valid_i = []
-        n_i_readyn = []
+        n_ready_in = []
         p_len = len(self.p)
         for i in range(p_len):
             r = self.stage.ispec() # input type
             r_data.append(r)
             data_valid.append(Signal(name="data_valid", reset_less=True))
             p_valid_i.append(Signal(name="p_valid_i", reset_less=True))
-            n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
+            n_ready_in.append(Signal(name="n_ready_in", reset_less=True))
             if hasattr(self.stage, "setup"):
                 self.stage.setup(m, r)
         if len(r_data) > 1:
             r_data = Array(r_data)
             p_valid_i = Array(p_valid_i)
-            n_i_readyn = Array(n_i_readyn)
+            n_ready_in = Array(n_ready_in)
             data_valid = Array(data_valid)
 
         nirn = Signal(reset_less=True)
-        m.d.comb += nirn.eq(~self.n.i_ready)
+        m.d.comb += nirn.eq(~self.n.ready_i)
         mid = self.p_mux.m_id
         for i in range(p_len):
             m.d.comb += data_valid[i].eq(0)
-            m.d.comb += n_i_readyn[i].eq(1)
+            m.d.comb += n_ready_in[i].eq(1)
             m.d.comb += p_valid_i[i].eq(0)
             m.d.comb += self.p[i].ready_o.eq(0)
         m.d.comb += p_valid_i[mid].eq(self.p_mux.active)
-        m.d.comb += self.p[mid].ready_o.eq(~data_valid[mid] | self.n.i_ready)
-        m.d.comb += n_i_readyn[mid].eq(nirn & data_valid[mid])
+        m.d.comb += self.p[mid].ready_o.eq(~data_valid[mid] | self.n.ready_i)
+        m.d.comb += n_ready_in[mid].eq(nirn & data_valid[mid])
         anyvalid = Signal(i, reset_less=True)
         av = []
         for i in range(p_len):
             av.append(data_valid[i])
         anyvalid = Cat(*av)
-        m.d.comb += self.n.o_valid.eq(anyvalid.bool())
+        m.d.comb += self.n.valid_o.eq(anyvalid.bool())
         m.d.comb += data_valid[mid].eq(p_valid_i[mid] | \
-                                    (n_i_readyn[mid] & data_valid[mid]))
+                                    (n_ready_in[mid] & data_valid[mid]))
 
         for i in range(p_len):
             vr = Signal(reset_less=True)
diff --git a/src/add/queue.py b/src/add/queue.py
index cb9e98e5..3411a739 100644
--- a/src/add/queue.py
+++ b/src/add/queue.py
@@ -67,8 +67,8 @@ class Queue(FIFOInterface, Elaboratable):
         p_valid_i = self.we
         enq_data = self.din
 
-        n_o_valid = self.readable
-        n_i_ready = self.re
+        n_valid_o = self.readable
+        n_ready_i = self.re
         deq_data = self.dout
 
         # intermediaries
@@ -94,10 +94,10 @@ class Queue(FIFOInterface, Elaboratable):
                      empty.eq(ptr_match & ~maybe_full),
                      full.eq(ptr_match & maybe_full),
                      do_enq.eq(p_ready_o & p_valid_i), # write conditions ok
-                     do_deq.eq(n_i_ready & n_o_valid), # read conditions ok
+                     do_deq.eq(n_ready_i & n_valid_o), # read conditions ok
 
                      # set readable and writable (NOTE: see pipe mode below)
-                     n_o_valid.eq(~empty), # cannot read if empty!
+                     n_valid_o.eq(~empty), # cannot read if empty!
                      p_ready_o.eq(~full),  # cannot write if full!
 
                      # set up memory and connect to input and output
@@ -128,17 +128,17 @@ class Queue(FIFOInterface, Elaboratable):
         # as Memory "write-through"... without relying on a changing API
         if self.fwft:
             with m.If(p_valid_i):
-                m.d.comb += n_o_valid.eq(1)
+                m.d.comb += n_valid_o.eq(1)
             with m.If(empty):
                 m.d.comb += deq_data.eq(enq_data)
                 m.d.comb += do_deq.eq(0)
-                with m.If(n_i_ready):
+                with m.If(n_ready_i):
                     m.d.comb += do_enq.eq(0)
 
         # pipe mode: if next stage says it's ready (readable), we
         #            *must* declare the input ready (writeable).
         if self.pipe:
-            with m.If(n_i_ready):
+            with m.If(n_ready_i):
                 m.d.comb += p_ready_o.eq(1)
 
         # set the count (available free space), optimise on power-of-two
diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 28a55996..e3e89167 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -135,8 +135,8 @@
         * outgoing previous-stage ready   (p.ready_o) is LOW
 
     output transmission conditions are when:
-        * outgoing next-stage strobe (n.o_valid) is HIGH
-        * outgoing next-stage ready   (n.i_ready) is LOW
+        * outgoing next-stage strobe (n.valid_o) is HIGH
+        * outgoing next-stage ready   (n.ready_i) is LOW
 
     the tricky bit is when the input has valid data and the output is not
     ready to accept it.  if it wasn't for the clock synchronisation, it
@@ -344,32 +344,32 @@ class PrevControl(Elaboratable):
 
 class NextControl(Elaboratable):
     """ contains the signals that go *to* the next stage (both in and out)
-        * o_valid: output indicating to next stage that data is valid
-        * i_ready: input from next stage indicating that it can accept data
+        * valid_o: output indicating to next stage that data is valid
+        * ready_i: input from next stage indicating that it can accept data
         * o_data : an output - added by the user of this class
     """
     def __init__(self, stage_ctl=False):
         self.stage_ctl = stage_ctl
-        self.o_valid = Signal(name="n_o_valid") # self out>>  next
-        self.i_ready = Signal(name="n_i_ready") # self <<in   next
+        self.valid_o = Signal(name="n_valid_o") # self out>>  next
+        self.ready_i = Signal(name="n_ready_i") # self <<in   next
         self.o_data = None # XXX MUST BE ADDED BY USER
         #if self.stage_ctl:
         self.d_valid = Signal(reset=1) # INTERNAL (data valid)
         self.trigger = Signal(reset_less=True)
 
     @property
-    def i_ready_test(self):
+    def ready_i_test(self):
         if self.stage_ctl:
-            return self.i_ready & self.d_valid
-        return self.i_ready
+            return self.ready_i & self.d_valid
+        return self.ready_i
 
     def connect_to_next(self, nxt):
         """ helper function to connect to the next stage data/valid/ready.
             data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
             use this when connecting stage-to-stage
         """
-        return [nxt.valid_i.eq(self.o_valid),
-                self.i_ready.eq(nxt.ready_o),
+        return [nxt.valid_i.eq(self.valid_o),
+                self.ready_i.eq(nxt.ready_o),
                 eq(nxt.i_data, self.o_data),
                ]
 
@@ -377,21 +377,21 @@ class NextControl(Elaboratable):
         """ internal helper function to connect stage to an output source.
             do not use to connect stage-to-stage!
         """
-        i_ready = nxt.i_ready if direct else nxt.i_ready_test
+        ready_i = nxt.ready_i if direct else nxt.ready_i_test
         o_data = fn(nxt.o_data) if fn is not None else nxt.o_data
-        return [nxt.o_valid.eq(self.o_valid),
-                self.i_ready.eq(i_ready),
+        return [nxt.valid_o.eq(self.valid_o),
+                self.ready_i.eq(ready_i),
                 eq(o_data, self.o_data),
                ]
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.trigger.eq(self.i_ready_test & self.o_valid)
+        m.d.comb += self.trigger.eq(self.ready_i_test & self.valid_o)
         return m
 
     def __iter__(self):
-        yield self.i_ready
-        yield self.o_valid
+        yield self.ready_i
+        yield self.valid_o
         if hasattr(self.o_data, "ports"):
             yield from self.o_data.ports()
         elif isinstance(self.o_data, Sequence):
@@ -788,8 +788,8 @@ class ControlBase(Elaboratable):
         m.d.comb += self.p.s_ready_o.eq(self.p._ready_o & self.stage.d_ready)
 
         # intercept the next (incoming) "ready" and combine it with data valid
-        sdv = self.stage.d_valid(self.n.i_ready)
-        m.d.comb += self.n.d_valid.eq(self.n.i_ready & sdv)
+        sdv = self.stage.d_valid(self.n.ready_i)
+        m.d.comb += self.n.d_valid.eq(self.n.ready_i & sdv)
 
         return m
 
@@ -801,8 +801,8 @@ class BufferedHandshake(ControlBase):
 
         Argument: stage.  see Stage API above
 
-        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
+        stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
                             process --->----^
@@ -832,7 +832,7 @@ class BufferedHandshake(ControlBase):
 
         # establish some combinatorial temporaries
         o_n_validn = Signal(reset_less=True)
-        n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
+        n_ready_i = Signal(reset_less=True, name="n_i_rdy_data")
         nir_por = Signal(reset_less=True)
         nir_por_n = Signal(reset_less=True)
         p_valid_i = Signal(reset_less=True)
@@ -841,12 +841,12 @@ class BufferedHandshake(ControlBase):
         por_pivn = Signal(reset_less=True)
         npnn = Signal(reset_less=True)
         self.m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
-                     o_n_validn.eq(~self.n.o_valid),
-                     n_i_ready.eq(self.n.i_ready_test),
-                     nir_por.eq(n_i_ready & self.p._ready_o),
-                     nir_por_n.eq(n_i_ready & ~self.p._ready_o),
-                     nir_novn.eq(n_i_ready | o_n_validn),
-                     nirn_novn.eq(~n_i_ready & o_n_validn),
+                     o_n_validn.eq(~self.n.valid_o),
+                     n_ready_i.eq(self.n.ready_i_test),
+                     nir_por.eq(n_ready_i & self.p._ready_o),
+                     nir_por_n.eq(n_ready_i & ~self.p._ready_o),
+                     nir_novn.eq(n_ready_i | o_n_validn),
+                     nirn_novn.eq(~n_ready_i & o_n_validn),
                      npnn.eq(nir_por | nirn_novn),
                      por_pivn.eq(self.p._ready_o & ~p_valid_i)
         ]
@@ -861,14 +861,14 @@ class BufferedHandshake(ControlBase):
         # data pass-through conditions
         with self.m.If(npnn):
             o_data = self._postprocess(result)
-            self.m.d.sync += [self.n.o_valid.eq(p_valid_i), # valid if p_valid
+            self.m.d.sync += [self.n.valid_o.eq(p_valid_i), # valid if p_valid
                               eq(self.n.o_data, o_data),    # update output
                              ]
         # buffer flush conditions (NOTE: can override data passthru conditions)
         with self.m.If(nir_por_n): # not stalled
             # Flush the [already processed] buffer to the output port.
             o_data = self._postprocess(r_data)
-            self.m.d.sync += [self.n.o_valid.eq(1),  # reg empty
+            self.m.d.sync += [self.n.valid_o.eq(1),  # reg empty
                               eq(self.n.o_data, o_data), # flush buffer
                              ]
         # output ready conditions
@@ -883,8 +883,8 @@ class SimpleHandshake(ControlBase):
 
         Argument: stage.  see Stage API above
 
-        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
+        stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
                               +--process->--^
@@ -926,11 +926,11 @@ class SimpleHandshake(ControlBase):
         result = _spec(self.stage.ospec, "r_tmp")
 
         # establish some combinatorial temporaries
-        n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
+        n_ready_i = Signal(reset_less=True, name="n_i_rdy_data")
         p_valid_i_p_ready_o = Signal(reset_less=True)
         p_valid_i = Signal(reset_less=True)
         m.d.comb += [p_valid_i.eq(self.p.valid_i_test),
-                     n_i_ready.eq(self.n.i_ready_test),
+                     n_ready_i.eq(self.n.ready_i_test),
                      p_valid_i_p_ready_o.eq(p_valid_i & self.p.ready_o),
         ]
 
@@ -944,16 +944,16 @@ class SimpleHandshake(ControlBase):
                          eq(self.n.o_data, o_data), # update output
                         ]
         # previous invalid or not ready, however next is accepting
-        with m.Elif(n_i_ready):
+        with m.Elif(n_ready_i):
             o_data = self._postprocess(result)
             m.d.sync += [eq(self.n.o_data, o_data)]
             # TODO: could still send data here (if there was any)
-            #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
+            #m.d.sync += self.n.valid_o.eq(0) # ...so set output invalid
             m.d.sync += r_busy.eq(0) # ...so set output invalid
 
-        m.d.comb += self.n.o_valid.eq(r_busy)
+        m.d.comb += self.n.valid_o.eq(r_busy)
         # if next is ready, so is previous
-        m.d.comb += self.p._ready_o.eq(n_i_ready)
+        m.d.comb += self.p._ready_o.eq(n_ready_i)
 
         return self.m
 
@@ -972,8 +972,8 @@ class UnbufferedPipeline(ControlBase):
 
         Argument: stage.  see Stage API, above
 
-        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
+        stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |
                             r_data        result
@@ -1039,10 +1039,10 @@ class UnbufferedPipeline(ControlBase):
         buf_full = Signal(reset_less=True)
         m.d.comb += p_valid_i.eq(self.p.valid_i_test)
         m.d.comb += pv.eq(self.p.valid_i & self.p.ready_o)
-        m.d.comb += buf_full.eq(~self.n.i_ready_test & data_valid)
+        m.d.comb += buf_full.eq(~self.n.ready_i_test & data_valid)
 
-        m.d.comb += self.n.o_valid.eq(data_valid)
-        m.d.comb += self.p._ready_o.eq(~data_valid | self.n.i_ready_test)
+        m.d.comb += self.n.valid_o.eq(data_valid)
+        m.d.comb += self.p._ready_o.eq(~data_valid | self.n.ready_i_test)
         m.d.sync += data_valid.eq(p_valid_i | buf_full)
 
         with m.If(pv):
@@ -1066,8 +1066,8 @@ class UnbufferedPipeline2(ControlBase):
 
         Argument: stage.  see Stage API, above
 
-        stage-1   p.valid_i >>in   stage   n.o_valid out>>   stage+1
-        stage-1   p.ready_o <<out  stage   n.i_ready <<in    stage+1
+        stage-1   p.valid_i >>in   stage   n.valid_o out>>   stage+1
+        stage-1   p.ready_o <<out  stage   n.ready_i <<in    stage+1
         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
                               |             |    |
                               +- process-> buf <-+
@@ -1123,9 +1123,9 @@ class UnbufferedPipeline2(ControlBase):
         p_valid_i = Signal(reset_less=True)
         m.d.comb += p_valid_i.eq(self.p.valid_i_test)
 
-        m.d.comb += self.n.o_valid.eq(buf_full | p_valid_i)
+        m.d.comb += self.n.valid_o.eq(buf_full | p_valid_i)
         m.d.comb += self.p._ready_o.eq(~buf_full)
-        m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
+        m.d.sync += buf_full.eq(~self.n.ready_i_test & self.n.valid_o)
 
         o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data))
         o_data = self._postprocess(o_data)
@@ -1190,8 +1190,8 @@ class PassThroughHandshake(ControlBase):
         m.d.comb += p_valid_i.eq(self.p.valid_i_test)
         m.d.comb += pvr.eq(p_valid_i & self.p.ready_o)
 
-        m.d.comb += self.p.ready_o.eq(~self.n.o_valid |  self.n.i_ready_test)
-        m.d.sync += self.n.o_valid.eq(p_valid_i       | ~self.p.ready_o)
+        m.d.comb += self.p.ready_o.eq(~self.n.valid_o |  self.n.ready_i_test)
+        m.d.sync += self.n.valid_o.eq(p_valid_i       | ~self.p.ready_o)
 
         odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
         m.d.sync += eq(r_data, odata)
@@ -1203,7 +1203,7 @@ class PassThroughHandshake(ControlBase):
 
 class RegisterPipeline(UnbufferedPipeline):
     """ A pipeline stage that delays by one clock cycle, creating a
-        sync'd latch out of o_data and o_valid as an indirect byproduct
+        sync'd latch out of o_data and valid_o as an indirect byproduct
         of using PassThroughStage
     """
     def __init__(self, iospecfn):
@@ -1275,8 +1275,8 @@ class FIFOControl(ControlBase):
                    ]
 
         # connect next rdy/valid/data - do cat on o_data
-        connections = [self.n.o_valid.eq(fifo.readable),
-                     fifo.re.eq(self.n.i_ready_test),
+        connections = [self.n.valid_o.eq(fifo.readable),
+                     fifo.re.eq(self.n.ready_i_test),
                    ]
         if self.fwft or self.buffered:
             m.d.comb += connections
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 898007dc..39d1f45f 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -37,22 +37,22 @@ from random import randint, seed
 
 
 def check_o_n_valid(dut, val):
-    o_n_valid = yield dut.n.o_valid
+    o_n_valid = yield dut.n.valid_o
     assert o_n_valid == val
 
 def check_o_n_valid2(dut, val):
-    o_n_valid = yield dut.n.o_valid
+    o_n_valid = yield dut.n.valid_o
     assert o_n_valid == val
 
 
 def tbench(dut):
     #yield dut.i_p_rst.eq(1)
-    yield dut.n.i_ready.eq(0)
+    yield dut.n.ready_i.eq(0)
     #yield dut.p.ready_o.eq(0)
     yield
     yield
     #yield dut.i_p_rst.eq(0)
-    yield dut.n.i_ready.eq(1)
+    yield dut.n.ready_i.eq(1)
     yield dut.p.i_data.eq(5)
     yield dut.p.valid_i.eq(1)
     yield
@@ -64,14 +64,14 @@ def tbench(dut):
 
     yield dut.p.i_data.eq(2)
     yield
-    yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
+    yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
     yield dut.p.i_data.eq(9)
     yield
     yield dut.p.valid_i.eq(0)
     yield dut.p.i_data.eq(12)
     yield
     yield dut.p.i_data.eq(32)
-    yield dut.n.i_ready.eq(1)
+    yield dut.n.ready_i.eq(1)
     yield
     yield from check_o_n_valid(dut, 1) # buffer still needs to output
     yield
@@ -83,12 +83,12 @@ def tbench(dut):
 
 def tbench2(dut):
     #yield dut.p.i_rst.eq(1)
-    yield dut.n.i_ready.eq(0)
+    yield dut.n.ready_i.eq(0)
     #yield dut.p.ready_o.eq(0)
     yield
     yield
     #yield dut.p.i_rst.eq(0)
-    yield dut.n.i_ready.eq(1)
+    yield dut.n.ready_i.eq(1)
     yield dut.p.i_data.eq(5)
     yield dut.p.valid_i.eq(1)
     yield
@@ -101,14 +101,14 @@ def tbench2(dut):
     yield dut.p.i_data.eq(2)
     yield
     yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
-    yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
+    yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
     yield dut.p.i_data.eq(9)
     yield
     yield dut.p.valid_i.eq(0)
     yield dut.p.i_data.eq(12)
     yield
     yield dut.p.i_data.eq(32)
-    yield dut.n.i_ready.eq(1)
+    yield dut.n.ready_i.eq(1)
     yield
     yield from check_o_n_valid2(dut, 1) # buffer still needs to output
     yield
@@ -158,10 +158,10 @@ class Test3:
             stall_range = randint(0, 3)
             for j in range(randint(1,10)):
                 stall = randint(0, stall_range) != 0
-                yield self.dut.n.i_ready.eq(stall)
+                yield self.dut.n.ready_i.eq(stall)
                 yield
-                o_n_valid = yield self.dut.n.o_valid
-                i_n_ready = yield self.dut.n.i_ready_test
+                o_n_valid = yield self.dut.n.valid_o
+                i_n_ready = yield self.dut.n.ready_i_test
                 if not o_n_valid or not i_n_ready:
                     continue
                 o_data = yield self.dut.n.o_data
@@ -234,10 +234,10 @@ class Test5:
             for j in range(randint(1,10)):
                 ready = randint(0, stall_range) != 0
                 #ready = True
-                yield self.dut.n.i_ready.eq(ready)
+                yield self.dut.n.ready_i.eq(ready)
                 yield
-                o_n_valid = yield self.dut.n.o_valid
-                i_n_ready = yield self.dut.n.i_ready_test
+                o_n_valid = yield self.dut.n.valid_o
+                i_n_ready = yield self.dut.n.ready_i_test
                 if not o_n_valid or not i_n_ready:
                     continue
                 if isinstance(self.dut.n.o_data, Record):
@@ -268,7 +268,7 @@ def tbench4(dut):
     while True:
         stall = randint(0, 3) != 0
         send = randint(0, 5) != 0
-        yield dut.n.i_ready.eq(stall)
+        yield dut.n.ready_i.eq(stall)
         o_p_ready = yield dut.p.ready_o
         if o_p_ready:
             if send and i != len(data):
@@ -278,8 +278,8 @@ def tbench4(dut):
             else:
                 yield dut.p.valid_i.eq(0)
         yield
-        o_n_valid = yield dut.n.o_valid
-        i_n_ready = yield dut.n.i_ready_test
+        o_n_valid = yield dut.n.valid_o
+        i_n_ready = yield dut.n.ready_i_test
         if o_n_valid and i_n_ready:
             o_data = yield dut.n.o_data
             assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
@@ -614,7 +614,7 @@ class ExampleStageDelayCls(StageCls, Elaboratable):
         return (self.count == 1)# | (self.count == 3)
         return Const(1)
 
-    def d_valid(self, i_ready):
+    def d_valid(self, ready_i):
         """ data is valid at output when this is true
         """
         return self.count == self.valid_trigger
@@ -1021,8 +1021,8 @@ if __name__ == '__main__':
         print ("test 2")
         dut = ExampleBufPipe2()
         run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
-        ports = [dut.p.valid_i, dut.n.i_ready,
-                 dut.n.o_valid, dut.p.ready_o] + \
+        ports = [dut.p.valid_i, dut.n.ready_i,
+                 dut.n.valid_o, dut.p.ready_o] + \
                  [dut.p.i_data] + [dut.n.o_data]
         vl = rtlil.convert(dut, ports=ports)
         with open("test_bufpipe2.il", "w") as f:
@@ -1053,8 +1053,8 @@ if __name__ == '__main__':
     test = Test5(dut, resultfn_6)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
 
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              list(dut.p.i_data) + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_ltcomb_pipe.il", "w") as f:
@@ -1064,8 +1064,8 @@ if __name__ == '__main__':
     dut = ExampleAddRecordPipe()
     data=data_dict()
     test = Test5(dut, resultfn_7, data=data)
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o,
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o,
              dut.p.i_data.src1, dut.p.i_data.src2,
              dut.n.o_data.src1, dut.n.o_data.src2]
     vl = rtlil.convert(dut, ports=ports)
@@ -1081,8 +1081,8 @@ if __name__ == '__main__':
 
     print ("test 9")
     dut = ExampleBufPipeChain2()
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpipechain2.il", "w") as f:
@@ -1113,8 +1113,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpipe12.il", "w") as f:
@@ -1125,8 +1125,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_unbufpipe13.il", "w") as f:
@@ -1137,8 +1137,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufunbuf15.il", "w") as f:
@@ -1149,8 +1149,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufunbuf16.il", "w") as f:
@@ -1161,8 +1161,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_unbufpipe17.il", "w") as f:
@@ -1173,8 +1173,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_identical, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_passthru18.il", "w") as f:
@@ -1185,8 +1185,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpass19.il", "w") as f:
@@ -1197,8 +1197,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_identical, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_fifo20.il", "w") as f:
@@ -1209,8 +1209,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_12, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_fifopass21.il", "w") as f:
@@ -1221,8 +1221,8 @@ if __name__ == '__main__':
     data=data_2op()
     test = Test5(dut, resultfn_8, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1234,8 +1234,8 @@ if __name__ == '__main__':
     data=data_2op()
     test = Test5(dut, resultfn_8, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1246,8 +1246,8 @@ if __name__ == '__main__':
     dut = FIFOTestRecordAddStageControl()
     data=data_2op()
     test = Test5(dut, resultfn_8, data=data)
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data.op1, dut.p.i_data.op2] + \
              [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
@@ -1260,8 +1260,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_add2pipe25.il", "w") as f:
@@ -1272,8 +1272,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpass997.il", "w") as f:
@@ -1284,8 +1284,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufpipe14.il", "w") as f:
@@ -1296,8 +1296,8 @@ if __name__ == '__main__':
     data = data_chain1()
     test = Test5(dut, resultfn_9, data=data)
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
-    ports = [dut.p.valid_i, dut.n.i_ready,
-             dut.n.o_valid, dut.p.ready_o] + \
+    ports = [dut.p.valid_i, dut.n.ready_i,
+             dut.n.valid_o, dut.p.ready_o] + \
              [dut.p.i_data] + [dut.n.o_data]
     vl = rtlil.convert(dut, ports=ports)
     with open("test_bufunbuf999.il", "w") as f:
diff --git a/src/add/test_fpadd_pipe.py b/src/add/test_fpadd_pipe.py
index a72244c4..67a6f9eb 100644
--- a/src/add/test_fpadd_pipe.py
+++ b/src/add/test_fpadd_pipe.py
@@ -79,13 +79,13 @@ class InputTest:
             #stall_range = randint(0, 3)
             #for j in range(randint(1,10)):
             #    stall = randint(0, stall_range) != 0
-            #    yield self.dut.n[0].i_ready.eq(stall)
+            #    yield self.dut.n[0].ready_i.eq(stall)
             #    yield
             n = self.dut.n[mid]
-            yield n.i_ready.eq(1)
+            yield n.ready_i.eq(1)
             yield
-            o_n_valid = yield n.o_valid
-            i_n_ready = yield n.i_ready
+            o_n_valid = yield n.valid_o
+            i_n_ready = yield n.ready_i
             if not o_n_valid or not i_n_ready:
                 continue
 
diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index 3ce8a96a..b6b2a9dc 100644
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -101,8 +101,8 @@ class FPDIVPipe(ControlBase):
         m.d.comb += self.p.ready_o.eq(self.fpdiv.in_a.ready_o)
         m.d.comb += self.fpdiv.in_a.valid_i.eq(self.p.valid_i_test)
 
-        m.d.comb += self.n.o_valid.eq(self.fpdiv.out_z.o_valid)
-        m.d.comb += self.fpdiv.out_z.i_ready.eq(self.n.i_ready_test)
+        m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
+        m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
         m.d.comb += self.n.o_data.eq(self.fpdiv.out_z.v)
 
         return m
diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 9ebcd8a7..a51ccf1a 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -103,13 +103,13 @@ class InputTest:
             #stall_range = randint(0, 3)
             #for j in range(randint(1,10)):
             #    stall = randint(0, stall_range) != 0
-            #    yield self.dut.n[0].i_ready.eq(stall)
+            #    yield self.dut.n[0].ready_i.eq(stall)
             #    yield
             n = self.dut.n[mid]
-            yield n.i_ready.eq(1)
+            yield n.ready_i.eq(1)
             yield
-            o_n_valid = yield n.o_valid
-            i_n_ready = yield n.i_ready
+            o_n_valid = yield n.valid_o
+            i_n_ready = yield n.ready_i
             if not o_n_valid or not i_n_ready:
                 continue
 
diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index ac25bbd2..bec958e5 100644
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -91,10 +91,10 @@ class OutputTest:
             count += 1
             assert count != 2000, "timeout: too long"
             n = self.dut.n[mid]
-            yield n.i_ready.eq(1)
+            yield n.ready_i.eq(1)
             yield
-            o_n_valid = yield n.o_valid
-            i_n_ready = yield n.i_ready
+            o_n_valid = yield n.valid_o
+            i_n_ready = yield n.ready_i
             if not o_n_valid or not i_n_ready:
                 continue
 
@@ -110,7 +110,7 @@ class OutputTest:
                 stall_range = randint(0, 3)
             stall = randint(0, stall_range) != 0
             if stall:
-                yield n.i_ready.eq(0)
+                yield n.ready_i.eq(0)
                 for i in range(stall_range):
                     yield
 
@@ -142,7 +142,7 @@ class TestSyncToPriorityPipe(Elaboratable):
         res = [self.p.valid_i, self.p.ready_o] + \
                 self.p.i_data.ports()
         for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
+            res += [self.n[i].ready_i, self.n[i].valid_o] + \
                     [self.n[i].o_data]
                     #self.n[i].o_data.ports()
         return res
diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 58848841..366986af 100644
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -164,13 +164,13 @@ class InputTest:
             #stall_range = randint(0, 3)
             #for j in range(randint(1,10)):
             #    stall = randint(0, stall_range) != 0
-            #    yield self.dut.n[0].i_ready.eq(stall)
+            #    yield self.dut.n[0].ready_i.eq(stall)
             #    yield
             n = self.dut.n
-            yield n.i_ready.eq(1)
+            yield n.ready_i.eq(1)
             yield
-            o_n_valid = yield n.o_valid
-            i_n_ready = yield n.i_ready
+            o_n_valid = yield n.valid_o
+            i_n_ready = yield n.ready_i
             if not o_n_valid or not i_n_ready:
                 continue
 
diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py
index c46e2391..2b0d9e56 100644
--- a/src/add/unit_test_single.py
+++ b/src/add/unit_test_single.py
@@ -60,16 +60,16 @@ def get_rs_case(dut, a, b, mid):
 
     yield in_b.valid_i.eq(0)
 
-    yield out_z.i_ready.eq(1)
+    yield out_z.ready_i.eq(1)
 
     while True:
-        out_z_stb = (yield out_z.o_valid)
+        out_z_stb = (yield out_z.valid_o)
         if not out_z_stb:
             yield
             continue
         vout_z = yield out_z.v
         #out_mid = yield dut.ids.out_mid
-        yield out_z.i_ready.eq(0)
+        yield out_z.ready_i.eq(0)
         yield
         break
 
@@ -106,16 +106,16 @@ def get_case(dut, a, b, mid):
 
     yield dut.in_b.valid_i.eq(0)
 
-    yield dut.out_z.i_ready.eq(1)
+    yield dut.out_z.ready_i.eq(1)
 
     while True:
-        out_z_stb = (yield dut.out_z.o_valid)
+        out_z_stb = (yield dut.out_z.valid_o)
         if not out_z_stb:
             yield
             continue
         out_z = yield dut.out_z.v
         #out_mid = yield dut.out_mid
-        yield dut.out_z.i_ready.eq(0)
+        yield dut.out_z.ready_i.eq(0)
         yield
         break
 
-- 
2.30.2