From 5a1bacb6f916d9a46a3d44830a4eb4bd3dca7d23 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Tue, 12 Nov 2019 15:44:17 +0000 Subject: [PATCH] aco: fix read_invocation with VGPR lane index MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler') --- src/amd/compiler/aco_instruction_selection.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index f616da9d88d..cdedb516542 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5626,9 +5626,8 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) } case nir_intrinsic_read_invocation: { Temp src = get_ssa_temp(ctx, instr->src[0].ssa); - Temp lane = get_ssa_temp(ctx, instr->src[1].ssa); + Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa)); Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); - assert(lane.regClass() == s1); if (src.regClass() == v1) { emit_wqm(ctx, bld.vop3(aco_opcode::v_readlane_b32, bld.def(s1), src, lane), dst); } else if (src.regClass() == v2) { -- 2.30.2