From 5a2ce64b2b6981f53bd55e37f65129e5446e0adc Mon Sep 17 00:00:00 2001 From: Kajol Jain Date: Wed, 12 Jun 2019 15:31:59 +0530 Subject: [PATCH] arch-power: Extra logs for debugging Change-Id: I701c422c180e5ade32675fc06b6ca0c3f91c64ef Signed-off-by: Kajol Jain --- src/arch/power/faults.hh | 2 +- src/arch/power/isa/decoder.isa | 2 ++ src/arch/power/system.cc | 3 +++ src/cpu/simple/atomic.cc | 6 +++--- src/cpu/simple_thread.hh | 2 ++ 5 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh index f73432696..1ea7c5487 100644 --- a/src/arch/power/faults.hh +++ b/src/arch/power/faults.hh @@ -233,7 +233,7 @@ class ProgramInterrupt : public PowerInterrupt virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst = StaticInst::nullStaticInstPtr ,uint64_t bitSet = 0) { - tc->setIntReg(INTREG_SRR0, tc->instAddr() + 4); + tc->setIntReg(INTREG_SRR0, tc->instAddr()); PowerInterrupt::updateSRR1(tc, bitSet); PowerInterrupt::updateMsr(tc); tc->pcState(ProgramPCSet); diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 3227d757e..edb4d5340 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -965,6 +965,7 @@ decode PO default Unknown::unknown() { ThreadContext *tc = xc->tcBase(); ThreadID t = tc->threadId(); if(bits(Rb_ud, 31, 27) == 0x5) { + printf("Get msgclr instr for threadid %d\n",(int)t); tc->getCpuPtr()->clearInterrupt(t, 7, 0); } }}); @@ -992,6 +993,7 @@ decode PO default Unknown::unknown() { Rb_ud,(int)tc->threadId()); uint64_t val2 = Rb_ud; printf("Reading done"); + printf("Msr value is 0x%016lx\n", MSR); if(bits(val1, 19, 0) == bits(val2, 19, 0)){ printf("Intterupt Happen\n"); t->getCpuPtr()->postInterrupt(i, 7, 0); diff --git a/src/arch/power/system.cc b/src/arch/power/system.cc index b54d3c4ec..db44eb58f 100644 --- a/src/arch/power/system.cc +++ b/src/arch/power/system.cc @@ -66,6 +66,9 @@ void PowerSystem::initState() { System::initState(); + printf("PowerSystem::initState: No of thread contexts %d\n" , + (int)threadContexts.size()); + ThreadContext *tc = threadContexts[0]; tc->pcState(tc->getSystemPtr()->kernelEntry); //Sixty Four, little endian,Hypervisor bits are enabled. diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 20c6e1cb6..b74e1dd42 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -412,7 +412,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, } dcache_access = true; - assert(!pkt.isError()); + //assert(!pkt.isError()); if (req->isLLSC()) { TheISA::handleLockedRead(thread, req); @@ -520,7 +520,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, threadSnoop(&pkt, curThread); } dcache_access = true; - assert(!pkt.isError()); + //assert(!pkt.isError()); if (req->isSwap()) { assert(res && curr_frag_id == 0); @@ -696,7 +696,7 @@ AtomicSimpleCPU::tick() icache_latency = sendPacket(icachePort, &ifetch_pkt); - assert(!ifetch_pkt.isError()); + // assert(!ifetch_pkt.isError()); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 5fe52cbd9..bd91398e2 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -286,6 +286,8 @@ class SimpleThread : public ThreadState, public ThreadContext readIntReg(RegIndex reg_idx) const override { int flatIndex = isa->flattenIntIndex(reg_idx); + if (flatIndex>TheISA::NumIntRegs) + printf("Flat index..%d NumIntRegs..%d\n",flatIndex,TheISA::NumIntRegs); assert(flatIndex < TheISA::NumIntRegs); uint64_t regVal(readIntRegFlat(flatIndex)); DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", -- 2.30.2