From 5a2f2d5e6f6eaa3209f47fea6bc6783df442cd40 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 14 Apr 2018 22:59:26 +0100 Subject: [PATCH] correct FILO --- simple_v_extension.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 71db85a13..fa576aa7e 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -9,7 +9,7 @@ a consistent "API" to parallelisation of existing *and future* operations. *Actual* internal hardware-level parallelism is *not* required, such that Simple-V may be viewed as providing a "compact" or "consolidated" means of issuing multiple near-identical arithmetic instructions to an -instruction FIFO, pending execution. +instruction queue (FILO), pending execution. *Actual* parallelism, if added independently of Simple-V in the form of Out-of-order restructuring (including parallel ALU lanes) or VLIW @@ -1098,7 +1098,7 @@ single-bit is less burdensome on instruction decode phase. ## Example Instruction translation: Instructions "ADD r2 r4 r4" would result in three instructions being -generated and placed into the FIFO: +generated and placed into the FILO: * ADD r2 r4 r4 * ADD r2 r5 r5 -- 2.30.2