From 5a3a995ab07354c6524ed6a880c97e5205e0046f Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Fri, 21 Oct 2022 13:11:39 +0100 Subject: [PATCH] fix(ls003.mdwn): Using desc from PowerISA as template for divmod2du --- openpower/sv/rfc/ls003.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index 7fb86463b..77416fd1e 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -191,6 +191,21 @@ Special registers altered: None +The 128-bit dividend is (RA) || (RC). The 64-bit divisor is +(RB). If the quotient can be represented in 64 bits, it is +placed into register RT. The modulo is placed into register RS. +RS is implictly defined as the same register as RC, similarly to maddedu. + +The instruction is only defined where both conditions are true: + +* (RA) < (RB) (unsigned comparison) +* (RB) is NOT 0 (not divide-by-0) + +If these conditions are not met, RT is set to all 1's, RS to all 0's. + +Both operands, quotient, and modulo are interpreted as unsigned integers. + + Divide/Modulo Quad-Double Unsigned is another VA-Form instruction that is near-identical to `divdeu` except that: -- 2.30.2