From 5a49cbe3f39084c33f05baa45b628a789057b6eb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 9 Sep 2022 01:47:00 +0100 Subject: [PATCH] clarify --- openpower/sv/rfc/ls001.mdwn | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 096759343..c7fccb84a 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -136,7 +136,8 @@ at least the next decade (including if added on VSX) **SPRs** * **SVSTATE** - Vectorisation State -* **SVSRR0** - identical in purpose to SRR0/1, storing SVSTATE on context-switch +* **SVSRR0** - identical in purpose to SRR0/1: storing SVSTATE on context-switch + along-side MSR and PC. * **SVSHAPE0-3** - these are 32-bit and may be grouped in pairs, they REMAP (shape) the Vectors * **SVLR** - again similar to LR for exactly the same purpose, SVSTATE @@ -145,7 +146,8 @@ at least the next decade (including if added on VSX) **Vector Management Instructions** -These fit into QTY 5of 6-bit XO 32-bit encoding: +These fit into QTY 5of 6-bit XO 32-bit encoding (svshape and svshape2 share +the same space): * **setvl** - Cray-style Scalar Vector Length instruction * **svstep** - used for Vertical-First Mode and for enquiring about internal -- 2.30.2