From 5a4ebac86b089d4edd6595c63adce925f502f7aa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 24 Jun 2019 14:05:22 +0100 Subject: [PATCH] add link --- simple_v_extension/specification.mdwn | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 30e1a8815..638ce711a 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -972,11 +972,14 @@ reshaping and offsets and so on. However it demonstrates the basic principle. Augmentations that produce the full pseudo-code are covered in other sections. -## SUBVL Pseudocode +## SUBVL Pseudocode -Adding in support for SUBVL is a matter of adding in an extra inner for-loop, where register src and dest are still incremented inside the inner part. Not that the predication is still taken from the VL index. +Adding in support for SUBVL is a matter of adding in an extra inner +for-loop, where register src and dest are still incremented inside the +inner part. Not that the predication is still taken from the VL index. -So whilst elements are indexed by (i * SUBVL + s), predicate bits are indexed by i +So whilst elements are indexed by "(i * SUBVL + s)", predicate bits are +indexed by "(i)" function op_add(rd, rs1, rs2) # add not VADD!  int i, id=0, irs1=0, irs2=0; -- 2.30.2