From 5a5fbe7f8de03420334049c1b305c3eff46adde7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 10:32:57 +0100 Subject: [PATCH] create new DivMulOutputData which does not have CA/CA32 --- src/soc/fu/common_output_stage.py | 2 +- src/soc/fu/div/pipe_data.py | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index cddf311f..5d5f0cb4 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -34,7 +34,7 @@ class CommonOutputStage(PipeModBase): # carry-out only if actually present in this input spec # (note: MUL and DIV do not have it, but ALU and Logical do) - if hasattr(self.i.xer_ca): + if hasattr(self.i, "xer_ca"): # Handle carry_out comb += self.o.xer_ca.data.eq(self.i.xer_ca.data) comb += self.o.xer_ca.ok.eq(op.output_carry) diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index 3a7f35d2..fa67aded 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -1,6 +1,6 @@ from nmigen import Signal, Const from soc.fu.pipe_data import IntegerData -from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec +from soc.fu.alu.pipe_data import CommonPipeSpec from soc.fu.logical.logical_input_record import CompLogicalOpSubset from ieee754.div_rem_sqrt_rsqrt.core import ( DivPipeCoreConfig, DivPipeCoreInputData, DP, @@ -17,8 +17,21 @@ class DIVInputData(IntegerData): self.a, self.b = self.ra, self.rb +# output stage shared between div and mul: like ALUOutputData but no CA/32 +class DivMulOutputData(IntegerData): + regspec = [('INT', 'o', '0:63'), + ('CR', 'cr_a', '0:3'), + ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32 + ('XER', 'xer_so', '32')] + def __init__(self, pspec): + super().__init__(pspec, True) + # convenience + self.cr0 = self.cr_a + + + class DIVPipeSpec(CommonPipeSpec): - regspec = (DIVInputData.regspec, ALUOutputData.regspec) + regspec = (DIVInputData.regspec, DivMulOutputData.regspec) opsubsetkls = CompLogicalOpSubset core_config = DivPipeCoreConfig( bit_width=64, -- 2.30.2