From 5a9e289624a64156bf503144eafb2bd0921493be Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 23 Feb 2017 12:12:25 -0800 Subject: [PATCH] Implement halt request. Also clean up some vestigial code. --- riscv/debug_module.h | 24 ------------------------ riscv/execute.cc | 3 +-- riscv/processor.cc | 12 ++++-------- 3 files changed, 5 insertions(+), 34 deletions(-) diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 76bcf01..e881776 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -75,26 +75,6 @@ class debug_module_t : public abstract_device_t bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); - void set_interrupt(uint32_t hartid) { - interrupt.insert(hartid); - } - void clear_interrupt(uint32_t hartid) { - interrupt.erase(hartid); - } - bool get_interrupt(uint32_t hartid) const { - return interrupt.find(hartid) != interrupt.end(); - } - - void set_halt_notification(uint32_t hartid) { - halt_notification.insert(hartid); - } - void clear_halt_notification(uint32_t hartid) { - halt_notification.erase(hartid); - } - bool get_halt_notification(uint32_t hartid) const { - return halt_notification.find(hartid) != halt_notification.end(); - } - // Debug Module Interface that the debugger (in our case through JTAG DTM) // uses to access the DM. // Return true for success, false for failure. @@ -105,10 +85,6 @@ class debug_module_t : public abstract_device_t static const unsigned progsize = 8; sim_t *sim; - // Track which interrupts from module to debugger are set. - std::set interrupt; - // Track which halt notifications from debugger to module are set. - std::set halt_notification; uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE]; uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE]; diff --git a/riscv/execute.cc b/riscv/execute.cc index 1e63cf0..0ac0e0a 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -63,8 +63,7 @@ bool processor_t::slow_path() void processor_t::step(size_t n) { if (state.dcsr.cause == DCSR_CAUSE_NONE) { - // TODO: get_interrupt() isn't super fast. Does that matter? - if (sim->debug_module.get_interrupt(id)) { + if (halt_request) { enter_debug_mode(DCSR_CAUSE_DEBUGINT); } else if (state.dcsr.halt) { enter_debug_mode(DCSR_CAUSE_HALT); diff --git a/riscv/processor.cc b/riscv/processor.cc index 13aeaa4..58837d1 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -609,19 +609,15 @@ reg_t processor_t::get_csr(int which) { uint32_t v = 0; v = set_field(v, DCSR_XDEBUGVER, 1); - v = set_field(v, DCSR_NDRESET, 0); - v = set_field(v, DCSR_FULLRESET, 0); - v = set_field(v, DCSR_PRV, state.dcsr.prv); - v = set_field(v, DCSR_STEP, state.dcsr.step); - v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id)); - v = set_field(v, DCSR_STOPCYCLE, 0); - v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm); v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh); v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks); v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku); - v = set_field(v, DCSR_HALT, state.dcsr.halt); + v = set_field(v, DCSR_STOPCYCLE, 0); + v = set_field(v, DCSR_STOPTIME, 0); v = set_field(v, DCSR_CAUSE, state.dcsr.cause); + v = set_field(v, DCSR_STEP, state.dcsr.step); + v = set_field(v, DCSR_PRV, state.dcsr.prv); return v; } case CSR_DPC: -- 2.30.2