From 5aa0ab1da7681952e5e6424800c0f80b84826695 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 11 Sep 2023 17:56:36 -0700 Subject: [PATCH] remove grev, leaving tests for later use with grevlut --- src/soc/fu/shift_rot/formal/proof_main_stage.py | 9 +++++++-- src/soc/fu/shift_rot/main_stage.py | 16 ---------------- 2 files changed, 7 insertions(+), 18 deletions(-) diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index 7ef3258f..379211d6 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -39,8 +39,9 @@ class TstOp(enum.Enum): RLCR = MicrOp.OP_RLCR EXTSWSLI = MicrOp.OP_EXTSWSLI TERNLOG = MicrOp.OP_TERNLOG - GREV32 = MicrOp.OP_GREV, 32 - GREV64 = MicrOp.OP_GREV, 64 + # grev removed -- leaving code for later use in grevlut + # GREV32 = MicrOp.OP_GREV, 32 + # GREV64 = MicrOp.OP_GREV, 64 @property def op(self): @@ -316,6 +317,7 @@ class Driver(Elaboratable): m.d.comb += Assert(dut.o.o.data[i] == lut[j]) m.d.comb += Assert(dut.o.xer_ca.data == 0) + # grev removed -- leaving code for later use in grevlut def _check_grev32(self, m, dut): m.d.comb += Assume(dut.i.ctx.op.is_32bit) # assert zero-extended @@ -326,6 +328,7 @@ class Driver(Elaboratable): m.d.comb += Assert((dut.o.o.data >> i)[0] == (dut.i.ra >> idx)[0]) m.d.comb += Assert(dut.o.xer_ca.data == 0) + # grev removed -- leaving code for later use in grevlut def _check_grev64(self, m, dut): m.d.comb += Assume(~dut.i.ctx.op.is_32bit) i = Signal(6) @@ -368,9 +371,11 @@ class ALUTestCase(FHDLTestCase): def test_ternlog(self): self.run_it(TstOp.TERNLOG) + @unittest.skip("grev removed -- leaving code for later use in grevlut") def test_grev32(self): self.run_it(TstOp.GREV32) + @unittest.skip("grev removed -- leaving code for later use in grevlut") def test_grev64(self): self.run_it(TstOp.GREV64) diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index 4f83a99d..27359278 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -12,7 +12,6 @@ from soc.fu.pipe_data import get_pspec_draft_bitmanip from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData, ShiftRotInputData) from nmutil.lut import BitwiseLut -from nmutil.grev import GRev from openpower.decoder.power_enums import MicrOp from soc.fu.shift_rot.rotator import Rotator @@ -41,24 +40,12 @@ class ShiftRotMainStage(PipeModBase): o = self.o.o bitwise_lut = None - grev = None if self.draft_bitmanip: bitwise_lut = BitwiseLut(input_count=3, width=XLEN) m.submodules.bitwise_lut = bitwise_lut comb += bitwise_lut.inputs[0].eq(self.i.rb) comb += bitwise_lut.inputs[1].eq(self.i.ra) comb += bitwise_lut.inputs[2].eq(self.i.rc) - # 6 == log2(64) because we have 64-bit values - grev = GRev(log2_width=(XLEN-1).bit_length()) - m.submodules.grev = grev - with m.If(op.is_32bit): - # 32-bit, so input is lower 32-bits zero-extended - comb += grev.input.eq(self.i.ra[0:32]) - # 32-bit, so we only feed in log2(32) == 5 bits - comb += grev.chunk_sizes.eq(self.i.rb[0:5]) - with m.Else(): - comb += grev.input.eq(self.i.ra) - comb += grev.chunk_sizes.eq(self.i.rb) # NOTE: the sh field immediate is read in by PowerDecode2 # (actually DecodeRB), whereupon by way of rb "immediate" mode @@ -120,9 +107,6 @@ class ShiftRotMainStage(PipeModBase): comb += bitwise_lut.lut.eq(self.fields.FormTLI.TLI[:]) comb += o.data.eq(bitwise_lut.output) comb += self.o.xer_ca.data.eq(0) - with m.Case(MicrOp.OP_GREV): - comb += o.data.eq(grev.output) - comb += self.o.xer_ca.data.eq(0) with m.Default(): comb += o.ok.eq(0) # otherwise disable -- 2.30.2