From 5b0f40c0fe398da57adb0f9bb7f72bf7f61b1987 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 8 Dec 2021 21:53:11 +0100 Subject: [PATCH] more work on test_loadstore1_ifetch_invalid() --- src/soc/experiment/test/test_loadstore1.py | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py index 64c3b6c6..e607e7a6 100644 --- a/src/soc/experiment/test/test_loadstore1.py +++ b/src/soc/experiment/test/test_loadstore1.py @@ -388,17 +388,7 @@ def _test_loadstore1(dut, mem): wbget.stop = True def _test_loadstore1_ifetch_invalid(dut, mem): - mmu = dut.submodules.mmu - pi = dut.submodules.ldst.pi - ldst = dut.submodules.ldst # to get at DAR (NOT part of PortInterface) - wbget.stop = False - - yield mmu.rin.prtbl.eq(0x1000000) # set process table - yield - - # TODO - - wbget.stop = True + ## TODO def test_loadstore1_ifetch(): @@ -453,7 +443,6 @@ def test_loadstore1_invalid(): sim.run() def test_loadstore1_ifetch_invalid(): - m, cmpi = setup_mmu() mem = {} @@ -462,14 +451,19 @@ def test_loadstore1_ifetch_invalid(): sim = Simulator(m) sim.add_clock(1e-6) + icache = m.submodules.ldst.icache sim.add_sync_process(wrap(_test_loadstore1_ifetch_invalid(m, mem))) + # add two wb_get processes onto the *same* memory dictionary. + # this shouuuld work.... cross-fingers... sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem))) - with sim.write_vcd('test_loadstore1_invalid.vcd'): + sim.add_sync_process(wrap(wb_get(icache.bus, mem))) + with sim.write_vcd('test_loadstore1_ifetch_invalid.vcd'): sim.run() + if __name__ == '__main__': test_loadstore1() test_loadstore1_invalid() test_loadstore1_ifetch() - test_loadstore1_ifetch_invalid() + #TODO:test_loadstore1_ifetch_invalid() -- 2.30.2