From 5b1b7fffb5bd6eb4155d6d8a366c5f925c142cc0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 16 Sep 2022 17:56:35 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/ls001.mdwn | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 16bcb1630..c709e2ecf 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -657,13 +657,14 @@ room to share PO9 (EXT009) with other potential uses.  A workaround for
 that is as follows:
 
 * EXT009, like EXT001 of Public v3.1, is **defined** as a 64-bit
-  encoding
-* bit 6 if 0b1 is 100% for Simple-V augmentation (Public v3.1 1.6.3)
-  "Defined Word" (aka EXT000-063), with the exception of 0x24000000
+  encoding. This makes Multi-Issue Length-identification trivial.
+* bit 6 if 0b1 is 100% for Simple-V augmentation of (Public v3.1 1.6.3)
+  "Defined Words" (aka EXT000-063), with the exception of 0x24000000
   as a Prefix, which is a new RESERVED encoding.
 * when bit 6 is 0b0 and bits 32-33 are 0b11 are **defined** as also
   allocated to Simple-V
-* all other patterns are `RESERVED` for other purposes, 
+* all other patterns are `RESERVED` for other purposes, outside the
+  scope of this RFC.
   
 | 0-5 | 6 | 7 | 8-31  | 32:33 |  Description               |
 |-----|---|---|-------|-------|---------------------------|
@@ -716,7 +717,8 @@ Where:
   in SVP64, even if the instruction is non-Vectoriseable.
 * Anything Vectorised-EXT000-063 is **automatically** being
   requested as 100% Reserved for every single "Defined Word"
-  (Public v3.1 1.6.3 definition). Vectorised-EXT001 is defined as illegal.
+  (Public v3.1 1.6.3 definition). Vectorised-EXT001 or EXT009
+  is defined as illegal.
 * Any **future** instruction
   added to EXT000-063 likewise, is **automatically**
   assigned corresponding reservations in the SVP64:EXT000-063
@@ -936,7 +938,6 @@ the Simple-V space.
 
 **illegal attempt to put Scalar EXT004 into Vector EXT2nn**
 
-
 | width | assembler | prefix?      | suffix    | description   |
 |-------|-----------|--------------|-----------|---------------|
 | 32bit | unallocated | none         | 0x10345678| scalar EXT0nn |
@@ -953,6 +954,20 @@ two MSBs are 0b11.  Thus this faulty attempt actually falls
 unintentionally
 into `RESERVED` "Non-Vectoriseable" Encoding space.
 
+**illegal attempt to put Scalar EXT001 into Vector space**
+
+| width | assembler | prefix?      | suffix    | description   |
+|-------|-----------|--------------|-----------|---------------|
+| 64bit | EXT001    | 0x04nnnnnn   | any       | scalar EXT001 |
+| 96bit | sv.EXT001 | 0x24!zero    | EXT001    | scalar SVP64Single:EXT001 |
+| 96bit | sv.EXT001 | 0x25nnnnnn   | EXT001    | vector SVP64:EXT001 |
+
+This becomes in effect an effort to define 96-bit instructions,
+which are illegal due to cost at the Decode Phase (Variable-Length
+Encoding). Likewise attempting to embed EXT009 (chained) is also
+illegal. The implications are clear unfortunately that all 64-bit
+EXT001 Scalar instructions are Unvectoriseable.
+
 \newpage{}
 # Use cases
 
-- 
2.30.2