From 5b4254bea20b8562872cc94b889fd0e18e0a41e1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 28 Sep 2020 16:53:23 +0100 Subject: [PATCH] connect SDRAM dqm to wrdata_mask --- src/soc/litex/florent/ls180soc.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 25da0a33..cd8119eb 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -224,11 +224,8 @@ class GENSDRPHY(Module): self.submodules.dq = SDRPad(pads, "dq", d.wrdata, d.wrdata_en, d.rddata) if hasattr(pads, "dm"): - # optimisation by yosys, fudge it... sigh - dm = Signal(len(pads.dm)) for i in range(len(pads.dm)): - self.comb += dm[i].eq(1) - self.sync += pads.dm[i].eq(dm[i]) # FIXME + self.specials += SDROutput(i=d.wrdata_mask[i], o=pads.dm[i]) # DQ/DM Control Path ---------------------------------------------- rddata_en = Signal(cl + cmd_latency) -- 2.30.2