From 5b6a8a80331226afd9cb55f30c706bad86eddf2e Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 4 May 2022 11:34:17 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 537e36fee..0100f588e 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -60,6 +60,23 @@ VL has been set to 4, and this is not supported. Likewise elwidth overrides if requested always raise illegal instruction traps. +**Full implementation (current revision) scenario** + +In this scenario, SVP64 is implemented as it stands in its entirety. +However a future revision or a competitor processor decides to also +implement portions of Quad-Precision VSX as SVP64-Vectorised. +Compatibility is **only** achieved if the earlier implementor raises +illegal instruction exceptions on **all** unimplemented opcodes within +the SVP64-Prefixed space, *even those marked by the Scalar Power ISA as +not needing to raise illegal instructions*. + +Additionally a future version of the specification adds a new feature, +requiring an additional SPR. This SPR was, at the time of implementation, +marked as "Reserved". The early implementation raises an illegal +instruction trap when this SPR is read or written, and consequently has +an opportunity to trap-and-emulate the full capability of the revised +version of the SVP64 Specification. + # XER, SO and other global flags Vector systems are expected to be high performance. This is achieved -- 2.30.2