From 5b6f0b56f90cfe871651ddfc414f718d5de77fb9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 5 Feb 2020 22:26:15 -0800 Subject: [PATCH] fastmodel,cpu,sim: Eliminate EndQuiesceEvent and plumbing. Change-Id: Ifca504bc298c09cbc16ef7cded21da455fb1e118 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25146 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/fastmodel/iris/thread_context.hh | 6 --- src/cpu/SConscript | 1 - src/cpu/checker/thread_context.hh | 7 --- src/cpu/o3/cpu.cc | 4 -- src/cpu/o3/thread_context.hh | 8 --- src/cpu/o3/thread_context_impl.hh | 1 - src/cpu/o3/thread_state.hh | 1 - src/cpu/quiesce_event.cc | 51 ------------------ src/cpu/quiesce_event.hh | 52 ------------------- src/cpu/simple_thread.cc | 4 -- src/cpu/simple_thread.hh | 6 --- src/cpu/thread_context.cc | 1 - src/cpu/thread_context.hh | 3 -- src/cpu/thread_state.cc | 13 +---- src/cpu/thread_state.hh | 4 -- src/sim/pseudo_inst.cc | 1 - 16 files changed, 1 insertion(+), 162 deletions(-) delete mode 100644 src/cpu/quiesce_event.cc delete mode 100644 src/cpu/quiesce_event.hh diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh index 5a4efd56d..8386e235e 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/thread_context.hh @@ -251,12 +251,6 @@ class ThreadContext : public ::ThreadContext void regStats(const std::string &name) override {} - EndQuiesceEvent * - getQuiesceEvent() override - { - panic("%s not implemented.", __FUNCTION__); - } - // Not necessarily the best location for these... // Having an extra function just to read these is obnoxious Tick diff --git a/src/cpu/SConscript b/src/cpu/SConscript index f1dc6bded..dea7e92a0 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -96,7 +96,6 @@ Source('inteltrace.cc') Source('intr_control.cc') Source('nativetrace.cc') Source('profile.cc') -Source('quiesce_event.cc') Source('reg_class.cc') Source('static_inst.cc') Source('simple_thread.cc') diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 18f4068d7..620522232 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -49,7 +49,6 @@ #include "cpu/thread_context.hh" #include "debug/Checker.hh" -class EndQuiesceEvent; namespace TheISA { class Decoder; @@ -213,12 +212,6 @@ class CheckerThreadContext : public ThreadContext checkerTC->regStats(name); } - EndQuiesceEvent * - getQuiesceEvent() override - { - return actualTC->getQuiesceEvent(); - } - Tick readLastActivate() override { return actualTC->readLastActivate(); } Tick readLastSuspend() override { return actualTC->readLastSuspend(); } diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 21bcf56c7..d9114903a 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -49,7 +49,6 @@ #include "cpu/checker/thread_context.hh" #include "cpu/o3/isa_specific.hh" #include "cpu/o3/thread_context.hh" -#include "cpu/quiesce_event.hh" #include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "debug/Activity.hh" @@ -340,9 +339,6 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) assert(o3_tc->cpu); o3_tc->thread = this->thread[tid]; - // Setup quiesce event. - this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); - // Give the thread the TC. this->thread[tid]->tc = tc; diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 042ad1c26..b1c47d2b9 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -46,8 +46,6 @@ #include "cpu/o3/isa_specific.hh" #include "cpu/thread_context.hh" -class EndQuiesceEvent; - /** * Derived ThreadContext class for use with the O3CPU. It * provides the interface for any external objects to access a @@ -441,12 +439,6 @@ class O3ThreadContext : public ThreadContext /** Reads the funcExeInst counter. */ Counter readFuncExeInst() const override { return thread->funcExeInst; } - /** Returns pointer to the quiesce event. */ - EndQuiesceEvent * - getQuiesceEvent() override - { - return this->thread->quiesceEvent; - } /** check if the cpu is currently in state update mode and squash if not. * This function will return true if a trap is pending or if a fault or * similar is currently writing to the thread context and doesn't want diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 034b9891d..588db15ef 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -46,7 +46,6 @@ #include "arch/registers.hh" #include "config/the_isa.hh" #include "cpu/o3/thread_context.hh" -#include "cpu/quiesce_event.hh" #include "debug/O3CPU.hh" template diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 030dc4ba2..76e201184 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -48,7 +48,6 @@ #include "sim/full_system.hh" #include "sim/sim_exit.hh" -class EndQuiesceEvent; class Event; class FunctionalMemory; class FunctionProfile; diff --git a/src/cpu/quiesce_event.cc b/src/cpu/quiesce_event.cc deleted file mode 100644 index 78a056d73..000000000 --- a/src/cpu/quiesce_event.cc +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "cpu/quiesce_event.hh" - -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "debug/Quiesce.hh" - -EndQuiesceEvent::EndQuiesceEvent(ThreadContext *_tc) - : tc(_tc) -{ -} - -void -EndQuiesceEvent::process() -{ - DPRINTF(Quiesce, "activating %s\n", tc->getCpuPtr()->name()); - tc->activate(); -} - -const char* -EndQuiesceEvent::description() const -{ - return "End Quiesce"; -} diff --git a/src/cpu/quiesce_event.hh b/src/cpu/quiesce_event.hh deleted file mode 100644 index d7db72073..000000000 --- a/src/cpu/quiesce_event.hh +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CPU_QUIESCE_EVENT_HH__ -#define __CPU_QUIESCE_EVENT_HH__ - -#include "sim/eventq.hh" - -class ThreadContext; - -/** Event for timing out quiesce instruction */ -class EndQuiesceEvent : public Event -{ - public: - /** A pointer to the thread context that is quiesced */ - ThreadContext *tc; - - EndQuiesceEvent(ThreadContext *_tc); - - /** Event process to occur at interrupt*/ - virtual void process(); - - /** Event description */ - virtual const char *description() const; -}; - -#endif // __CPU_QUIESCE_EVENT_HH__ diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 20ada332c..8f2ab54c8 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -52,7 +52,6 @@ #include "config/the_isa.hh" #include "cpu/base.hh" #include "cpu/profile.hh" -#include "cpu/quiesce_event.hh" #include "cpu/thread_context.hh" #include "mem/se_translating_port_proxy.hh" #include "mem/translating_port_proxy.hh" @@ -78,7 +77,6 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, { assert(isa); clearArchRegs(); - quiesceEvent = new EndQuiesceEvent(this); } SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, @@ -91,8 +89,6 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, { assert(isa); - quiesceEvent = new EndQuiesceEvent(this); - clearArchRegs(); if (baseCpu->params()->profile) { diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 9e6a2a71b..d62fa0eb5 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -249,12 +249,6 @@ class SimpleThread : public ThreadState, public ThreadContext /// Set the status to Halted. void halt() override; - EndQuiesceEvent * - getQuiesceEvent() override - { - return ThreadState::getQuiesceEvent(); - } - Tick readLastActivate() override { diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index 5c194dff0..d1d89df14 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -46,7 +46,6 @@ #include "base/trace.hh" #include "config/the_isa.hh" #include "cpu/base.hh" -#include "cpu/quiesce_event.hh" #include "debug/Context.hh" #include "debug/Quiesce.hh" #include "params/BaseCPU.hh" diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index fdd6b8a53..6ebb191bd 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -64,7 +64,6 @@ class BaseCPU; class BaseTLB; class CheckerCPU; class Checkpoint; -class EndQuiesceEvent; class PortProxy; class Process; class System; @@ -184,8 +183,6 @@ class ThreadContext : public PCEventScope virtual void regStats(const std::string &name) {}; - virtual EndQuiesceEvent *getQuiesceEvent() = 0; - virtual void scheduleInstCountEvent(Event *event, Tick count) = 0; virtual void descheduleInstCountEvent(Event *event) = 0; virtual Tick getCurrentInstCount() = 0; diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index 741d119b4..f4859f6d6 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -31,7 +31,6 @@ #include "base/output.hh" #include "cpu/base.hh" #include "cpu/profile.hh" -#include "cpu/quiesce_event.hh" #include "mem/port.hh" #include "mem/port_proxy.hh" #include "mem/se_translating_port_proxy.hh" @@ -44,7 +43,7 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process) : numInst(0), numOp(0), numLoad(0), startNumLoad(0), _status(ThreadContext::Halted), baseCpu(cpu), _contextId(0), _threadId(_tid), lastActivate(0), lastSuspend(0), - profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), + profile(NULL), profileNode(NULL), profilePC(0), process(_process), physProxy(NULL), virtProxy(NULL), funcExeInst(0), storeCondFailures(0) { @@ -67,11 +66,6 @@ ThreadState::serialize(CheckpointOut &cp) const if (!FullSystem) return; - - Tick quiesceEndTick = 0; - if (quiesceEvent->scheduled()) - quiesceEndTick = quiesceEvent->when(); - SERIALIZE_SCALAR(quiesceEndTick); } void @@ -84,11 +78,6 @@ ThreadState::unserialize(CheckpointIn &cp) if (!FullSystem) return; - - Tick quiesceEndTick; - UNSERIALIZE_SCALAR(quiesceEndTick); - if (quiesceEndTick) - baseCpu->schedule(quiesceEvent, quiesceEndTick); } void diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 1bbf4464f..e3f68b19a 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -36,7 +36,6 @@ #include "cpu/thread_context.hh" #include "sim/process.hh" -class EndQuiesceEvent; class FunctionProfile; class ProfileNode; @@ -85,8 +84,6 @@ struct ThreadState : public Serializable { void dumpFuncProfile(); - EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; } - void profileClear(); void profileSample(); @@ -159,7 +156,6 @@ struct ThreadState : public Serializable { FunctionProfile *profile; ProfileNode *profileNode; Addr profilePC; - EndQuiesceEvent *quiesceEvent; protected: Process *process; diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 0e7ae9859..8c662c657 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -55,7 +55,6 @@ #include "base/output.hh" #include "config/the_isa.hh" #include "cpu/base.hh" -#include "cpu/quiesce_event.hh" #include "cpu/thread_context.hh" #include "debug/Loader.hh" #include "debug/Quiesce.hh" -- 2.30.2