From 5b78bd8451e6dd6a9eca059a85c52778e6d641bc Mon Sep 17 00:00:00 2001 From: Henry Styles Date: Mon, 7 Aug 2017 17:34:01 -0700 Subject: [PATCH] U500VC707DevKit 4GB DIMM support --- .../xilinxvc707mig/XilinxVC707MIG.scala | 37 +++++++++++++------ .../XilinxVC707MIGPeriphery.scala | 12 ++++-- .../scala/ip/xilinx/vc707mig/vc707mig.scala | 21 +++++++---- 3 files changed, 48 insertions(+), 22 deletions(-) diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index afaff33..5351cf0 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -10,20 +10,30 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig} -trait HasXilinxVC707MIGParameters { -} +case class XilinxVC707MIGParams( + address : Seq[AddressSet] +) -class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR +class XilinxVC707MIGPads(depth : BigInt) extends VC707MIGIODDR(depth) { + def this(c : XilinxVC707MIGParams) { + this(AddressRange.fromSets(c.address).head.size) + } +} -class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR - with VC707MIGIOClocksReset +class XilinxVC707MIGIO(depth : BigInt) extends VC707MIGIODDR(depth) with VC707MIGIOClocksReset -class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters { +class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule { + val ranges = AddressRange.fromSets(c.address) + require (ranges.size == 1, "DDR range must be contiguous") + val offset = ranges.head.base + val depth = ranges.head.size + require((depth==0x40000000L) || (depth==0x100000000L)) //1GB or 4GB depth + val device = new MemoryDevice val node = TLInputNode() val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)), + slaves = Seq(AXI4SlaveParameters( + address = c.address, resources = device.reg, regionType = RegionType.UNCACHED, executable = true, @@ -48,12 +58,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC lazy val module = new LazyModuleImp(this) { val io = new Bundle { - val port = new XilinxVC707MIGIO + val port = new XilinxVC707MIGIO(depth) val tl = node.bundleIn } //MIG black box instantiation - val blackbox = Module(new vc707mig) + val blackbox = Module(new vc707mig(depth)) //pins to top level @@ -102,9 +112,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC //app_ref_ack := unconnected //app_zq_ack := unconnected + val awaddr = axi_async.aw.bits.addr - UInt(offset) + val araddr = axi_async.ar.bits.addr - UInt(offset) + //slave AXI interface write address ports blackbox.io.s_axi_awid := axi_async.aw.bits.id - blackbox.io.s_axi_awaddr := axi_async.aw.bits.addr //truncation ?? + blackbox.io.s_axi_awaddr := awaddr //truncated blackbox.io.s_axi_awlen := axi_async.aw.bits.len blackbox.io.s_axi_awsize := axi_async.aw.bits.size blackbox.io.s_axi_awburst := axi_async.aw.bits.burst @@ -130,7 +143,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC //slave AXI interface read address ports blackbox.io.s_axi_arid := axi_async.ar.bits.id - blackbox.io.s_axi_araddr := axi_async.ar.bits.addr //truncation ?? + blackbox.io.s_axi_araddr := araddr // truncated blackbox.io.s_axi_arlen := axi_async.ar.bits.len blackbox.io.s_axi_arsize := axi_async.ar.bits.size blackbox.io.s_axi_arburst := axi_async.ar.bits.burst diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala index 068f64c..7aebfae 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala @@ -2,13 +2,16 @@ package sifive.blocks.devices.xilinxvc707mig import Chisel._ +import freechips.rocketchip.config._ import freechips.rocketchip.coreplex.HasMemoryBus -import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange} + +case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams] trait HasMemoryXilinxVC707MIG extends HasMemoryBus { val module: HasMemoryXilinxVC707MIGModuleImp - val xilinxvc707mig = LazyModule(new XilinxVC707MIG) + val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey))) require(nMemoryChannels == 1, "Coreplex must have 1 master memory port") xilinxvc707mig.node := memBuses.head.toDRAMController @@ -24,7 +27,10 @@ trait HasMemoryXilinxVC707MIGBundle { trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp with HasMemoryXilinxVC707MIGBundle { val outer: HasMemoryXilinxVC707MIG - val xilinxvc707mig = IO(new XilinxVC707MIGIO) + val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) + require (ranges.size == 1, "DDR range must be contiguous") + val depth = ranges.head.size + val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth)) xilinxvc707mig <> outer.xilinxvc707mig.module.io.port } diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala index 1e01748..7b9ace3 100644 --- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala +++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala @@ -3,13 +3,15 @@ package sifive.blocks.ip.xilinx.vc707mig import Chisel._ import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.util.GenericParameterizedBundle import freechips.rocketchip.config._ // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0 // Black Box -trait VC707MIGIODDR extends Bundle { - val ddr3_addr = Bits(OUTPUT,14) +class VC707MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { + require((depth==0x40000000L) || (depth==0x100000000L),"VC707MIGIODDR supports 1GB and 4GB depth configuraton only") + val ddr3_addr = Bits(OUTPUT,if(depth==0x40000000L) 14 else 16) val ddr3_ba = Bits(OUTPUT,3) val ddr3_ras_n = Bool(OUTPUT) val ddr3_cas_n = Bool(OUTPUT) @@ -44,10 +46,15 @@ trait VC707MIGIOClocksReset extends Bundle { //scalastyle:off //turn off linter: blackbox name must match verilog module -class vc707mig(implicit val p:Parameters) extends BlackBox +class vc707mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox { - val io = new Bundle with VC707MIGIODDR - with VC707MIGIOClocksReset { + private val oneGB : BigInt = 0x40000000L + private val fourGB : BigInt = 0x100000000L + require((depth==oneGB) || (depth==fourGB),"vc707mig supports 1GB and 4GB depth configuraton only") + + override def desiredName = if(depth==fourGB) "vc707mig4gb" else "vc707mig" + + val io = new VC707MIGIODDR(depth) with VC707MIGIOClocksReset { // User interface signals val app_sr_req = Bool(INPUT) val app_ref_req = Bool(INPUT) @@ -58,7 +65,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox //axi_s //slave interface write address ports val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,30) + val s_axi_awaddr = Bits(INPUT,if(depth==oneGB) 30 else 32) val s_axi_awlen = Bits(INPUT,8) val s_axi_awsize = Bits(INPUT,3) val s_axi_awburst = Bits(INPUT,2) @@ -81,7 +88,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox val s_axi_bvalid = Bool(OUTPUT) //slave interface read address ports val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,30) + val s_axi_araddr = Bits(INPUT,if(depth==oneGB) 30 else 32) val s_axi_arlen = Bits(INPUT,8) val s_axi_arsize = Bits(INPUT,3) val s_axi_arburst = Bits(INPUT,2) -- 2.30.2