From 5b9033225f35f60821e1b72e7f37acbf195936fa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 29 Mar 2019 19:37:51 +0000 Subject: [PATCH] add generate to nmigen_add_experiment.py again --- src/add/nmigen_add_experiment.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index 84e6790c..ecb1d35b 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -2,6 +2,27 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 +from nmigen.cli import main, verilog from fpadd.statemachine import FPADDBase, FPADD from fpadd.pipeline import FPADDMuxInOut +if __name__ == "__main__": + if True: + alu = FPADD(width=32, id_wid=5, single_cycle=True) + main(alu, ports=alu.rs[0][0].ports() + \ + alu.rs[0][1].ports() + \ + alu.res[0].ports() + \ + [alu.ids.in_mid, alu.ids.out_mid]) + else: + alu = FPADDBase(width=32, id_wid=5, single_cycle=True) + main(alu, ports=[alu.in_a, alu.in_b] + \ + alu.in_t.ports() + \ + alu.out_z.ports() + \ + [alu.in_mid, alu.out_mid]) + + + # works... but don't use, just do "python fname.py convert -t v" + #print (verilog.convert(alu, ports=[ + # ports=alu.in_a.ports() + \ + # alu.in_b.ports() + \ + # alu.out_z.ports()) -- 2.30.2