From 5b90fe712949d7ff0d8417d5fe8b9b3e6c2ced70 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 25 Dec 2020 20:06:15 +0000 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index ef5357a8d..58e6e2e54 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -768,6 +768,12 @@ Note that RC1 Mode basically turns all operations into `cmp`. The calculation i Note that predication is still respected: predicate zeroing is slightly different: elements that fail the CR test *or* are masked out are zero'd. +### pred-result mode on CR ops + +Yes, really: CR operations (mtcr, crand, cror) may be Vectorised, predicated, and also pred-result mode applied to it. In this case, the Vectorisation applies to the batch of 4 bits, i.e. it is not the CR individual bits that are treated as the Vector, but the CRs themselves (CR0, CR8, CR9...) + +Thus after each Vectorised operation (crand) a test of the CR result can in fact be performed. + ## CR Operations CRs are slightly more involved than INT or FP registers due to the -- 2.30.2