From 5bb90038d6820e42f8dfbd9803294405f56db1cf Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Fri, 5 Mar 2021 17:47:53 +0100 Subject: [PATCH] unit test: pass bool mmu --- src/soc/decoder/isa/test_caller.py | 5 +++-- src/soc/decoder/isa/test_caller_radix.py | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 691d9a71..6863fff3 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -16,7 +16,7 @@ class Register: def __init__(self, num): self.num = num -def run_tst(generator, initial_regs, initial_sprs=None, svstate=0): +def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False): if initial_sprs is None: initial_sprs = {} m = Module() @@ -34,7 +34,8 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0): initial_insns=gen, respect_pc=True, initial_svstate=svstate, disassembly=insncode, - bigendian=0) + bigendian=0, + mmu=mmu) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py index 9b92cf81..a892e4c1 100644 --- a/src/soc/decoder/isa/test_caller_radix.py +++ b/src/soc/decoder/isa/test_caller_radix.py @@ -26,7 +26,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) def run_tst_program(self, prog, initial_regs=[0] * 32): - simulator = run_tst(prog, initial_regs) + simulator = run_tst(prog, initial_regs,mmu=True) simulator.gpr.dump() return simulator -- 2.30.2