From 5bc1ded6378cc98379d35e1e87179e14240f697a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 24 Sep 2020 21:17:05 +0100 Subject: [PATCH] do not have to use uart_litex gpio_litex names --- src/soc/litex/florent/libresoc/ls180.py | 6 +++--- src/soc/litex/florent/ls180soc.py | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py index b7e01ccd..a98c639b 100644 --- a/src/soc/litex/florent/libresoc/ls180.py +++ b/src/soc/litex/florent/libresoc/ls180.py @@ -112,15 +112,15 @@ _io = [ n_gpio = 16 # 16 GPIOs -_io.append( make_gpio("gpio_litex", 0, n_gpio) ) +_io.append( make_gpio("gpio", 0, n_gpio) ) # EINT: 3 pins _io.append( ("eint", 3, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) ) # UART0: 2 pins -_io.append(make_uart("uart_litex", 0)) +_io.append(make_uart("uart", 0)) # UART1: 2 pins -_io.append(make_uart("uart_litex", 1)) +_io.append(make_uart("uart", 1)) # Platform ----------------------------------------------------------------------------------------- diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 21ecbb4c..9c7547f7 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -251,7 +251,7 @@ class LibreSoCSim(SoCCore): uart_name = "sim" elif platform == 'ls180': platform = LS180Platform() - uart_name = "uart_litex" + uart_name = "uart" #cpu_data_width = 32 cpu_data_width = 64 @@ -386,7 +386,7 @@ class LibreSoCSim(SoCCore): self.submodules.gpio = GPIOTristateASIC(gpio_core_pads) self.add_csr("gpio") - gpio_pads = platform.request("gpio_litex") + gpio_pads = platform.request("gpio") gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads self.comb += gpio_pads.i.eq(gpio_io_pads.i) self.comb += gpio_io_pads.o.eq(gpio_pads.o) -- 2.30.2