From 5bda1ff1bec0e01300a4e8e3da38168958df9ebc Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Tue, 14 Apr 2015 17:45:40 -0700 Subject: [PATCH] i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_fs.h | 1 + .../drivers/dri/i965/brw_fs_generator.cpp | 116 +++++++++--------- 2 files changed, 58 insertions(+), 59 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index c42907050d0..1d3f83d9cdd 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -639,6 +639,7 @@ private: bool patch_discard_jumps_to_fb_writes(); struct brw_context *brw; + const struct brw_device_info *devinfo; struct brw_compile *p; const void * const key; diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 1ef2d1d5aa9..ce5ad8369f6 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -130,14 +130,14 @@ fs_generator::fs_generator(struct brw_context *brw, bool runtime_check_aads_emit, const char *stage_abbrev) - : brw(brw), key(key), + : brw(brw), devinfo(brw->intelScreen->devinfo), key(key), prog_data(prog_data), prog(prog), promoted_constants(promoted_constants), runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false), stage_abbrev(stage_abbrev), mem_ctx(mem_ctx) { p = rzalloc(mem_ctx, struct brw_compile); - brw_init_compile(brw->intelScreen->devinfo, p, mem_ctx); + brw_init_compile(devinfo, p, mem_ctx); } fs_generator::~fs_generator() @@ -159,7 +159,7 @@ public: bool fs_generator::patch_discard_jumps_to_fb_writes() { - if (brw->gen < 6 || this->discard_halt_patches.is_empty()) + if (devinfo->gen < 6 || this->discard_halt_patches.is_empty()) return false; int scale = brw_jump_scale(p->devinfo); @@ -203,7 +203,7 @@ fs_generator::fire_fb_write(fs_inst *inst, brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; - if (brw->gen < 6) { + if (devinfo->gen < 6) { brw_push_insn_state(p); brw_set_default_exec_size(p, BRW_EXECUTE_8); brw_set_default_mask_control(p, BRW_MASK_DISABLE); @@ -254,7 +254,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key; struct brw_reg implied_header; - if (brw->gen < 8 && !brw->is_haswell) { + if (devinfo->gen < 8 && !devinfo->is_haswell) { brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); } @@ -277,7 +277,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) if (prog_data->uses_kill) { struct brw_reg pixel_mask; - if (brw->gen >= 6) + if (devinfo->gen >= 6) pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); else pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); @@ -285,7 +285,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) brw_MOV(p, pixel_mask, brw_flag_reg(0, 1)); } - if (brw->gen >= 6) { + if (devinfo->gen >= 6) { brw_push_insn_state(p); brw_set_default_exec_size(p, BRW_EXECUTE_16); brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED); @@ -325,7 +325,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload) fire_fb_write(inst, payload, implied_header, inst->mlen); } else { /* This can only happen in gen < 6 */ - assert(brw->gen < 6); + assert(devinfo->gen < 6); struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); @@ -413,8 +413,8 @@ fs_generator::generate_linterp(fs_inst *inst, struct brw_reg delta_y = offset(src[0], dispatch_width / 8); struct brw_reg interp = src[1]; - if (brw->has_pln && - (brw->gen >= 7 || (delta_x.nr & 1) == 0)) { + if (devinfo->has_pln && + (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) { brw_PLN(p, dst, interp, delta_x); } else { brw_LINE(p, brw_null_reg(), interp, delta_x); @@ -531,7 +531,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src unreachable("Invalid width for texture instruction"); } - if (brw->gen >= 5) { + if (devinfo->gen >= 5) { switch (inst->opcode) { case SHADER_OPCODE_TEX: if (inst->shadow_compare) { @@ -560,7 +560,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src case SHADER_OPCODE_TXD: if (inst->shadow_compare) { /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */ - assert(brw->gen >= 8 || brw->is_haswell); + assert(devinfo->gen >= 8 || devinfo->is_haswell); msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; } else { msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; @@ -570,17 +570,17 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; break; case SHADER_OPCODE_TXF_CMS: - if (brw->gen >= 7) + if (devinfo->gen >= 7) msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS; else msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; break; case SHADER_OPCODE_TXF_UMS: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS; break; case SHADER_OPCODE_TXF_MCS: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS; break; case SHADER_OPCODE_LOD: @@ -588,15 +588,15 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src break; case SHADER_OPCODE_TG4: if (inst->shadow_compare) { - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C; } else { - assert(brw->gen >= 6); + assert(devinfo->gen >= 6); msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4; } break; case SHADER_OPCODE_TG4_OFFSET: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); if (inst->shadow_compare) { msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C; } else { @@ -679,11 +679,11 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src } if (is_combined_send) { - assert(brw->gen >= 9 || brw->is_cherryview); + assert(devinfo->gen >= 9 || devinfo->is_cherryview); rlen = 0; } - assert(brw->gen < 7 || !inst->header_present || + assert(devinfo->gen < 7 || !inst->header_present || src.file == BRW_GENERAL_REGISTER_FILE); assert(sampler_index.type == BRW_REGISTER_TYPE_UD); @@ -693,13 +693,13 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src * Otherwise, we can use an implied move from g0 to the first message reg. */ if (inst->header_present) { - if (brw->gen < 6 && !inst->offset) { + if (devinfo->gen < 6 && !inst->offset) { /* Set up an implied move from g0 to the MRF. */ src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); } else { struct brw_reg header_reg; - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { header_reg = src; } else { assert(inst->base_mrf != -1); @@ -890,7 +890,7 @@ fs_generator::generate_ddy(enum opcode opcode, */ bool unroll_to_simd8 = (dispatch_width == 16 && - (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell))); + (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell))); /* produce accurate derivatives */ struct brw_reg src0 = brw_reg(src.file, src.nr, 0, @@ -953,7 +953,7 @@ fs_generator::generate_ddy(enum opcode opcode, void fs_generator::generate_discard_jump(fs_inst *inst) { - assert(brw->gen >= 6); + assert(devinfo->gen >= 6); /* This HALT will be patched up at FB write time to point UIP at the end of * the program, and at brw_uip_jip() JIP will be set to the end of the @@ -1039,7 +1039,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, bool header_present = false; int mlen = 1; - if (brw->gen >= 9) { + if (devinfo->gen >= 9) { /* Skylake requires a message header in order to use SIMD4x2 mode. */ src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD); mlen = 2; @@ -1122,7 +1122,7 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg index, struct brw_reg offset) { - assert(brw->gen < 7); /* Should use the gen7 variant. */ + assert(devinfo->gen < 7); /* Should use the gen7 variant. */ assert(inst->header_present); assert(inst->mlen); @@ -1139,7 +1139,7 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst, rlen = 4; } - if (brw->gen >= 5) + if (devinfo->gen >= 5) msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; else { /* We always use the SIMD16 message so that we only have to load U, and @@ -1163,7 +1163,7 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst, brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE); brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW)); brw_set_src0(p, send, header); - if (brw->gen < 6) + if (devinfo->gen < 6) brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf); /* Our surface is set up as floats, regardless of what actual data is @@ -1189,7 +1189,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst, struct brw_reg index, struct brw_reg offset) { - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); /* Varying-offset pull constant loads are treated as a normal expression on * gen7, so the fact that it's a send message is hidden at the IR level. */ @@ -1276,7 +1276,7 @@ fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst) struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg); struct brw_reg dispatch_mask; - if (brw->gen >= 6) + if (devinfo->gen >= 6) dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); else dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); @@ -1395,7 +1395,7 @@ fs_generator::generate_pack_half_2x16_split(fs_inst *inst, struct brw_reg x, struct brw_reg y) { - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); assert(dst.type == BRW_REGISTER_TYPE_UD); assert(x.type == BRW_REGISTER_TYPE_F); assert(y.type == BRW_REGISTER_TYPE_F); @@ -1433,7 +1433,7 @@ fs_generator::generate_unpack_half_2x16_split(fs_inst *inst, struct brw_reg dst, struct brw_reg src) { - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); assert(dst.type == BRW_REGISTER_TYPE_F); assert(src.type == BRW_REGISTER_TYPE_UD); @@ -1463,7 +1463,7 @@ fs_generator::generate_shader_time_add(fs_inst *inst, struct brw_reg offset, struct brw_reg value) { - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); brw_push_insn_state(p); brw_set_default_mask_control(p, true); @@ -1537,8 +1537,6 @@ fs_generator::enable_debug(const char *shader_name) int fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) { - const struct brw_device_info *devinfo = brw->intelScreen->devinfo; - /* align to 64 byte boundary. */ while (p->next_insn_offset % 64) brw_NOP(p); @@ -1632,7 +1630,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case BRW_OPCODE_MAD: - assert(brw->gen >= 6); + assert(devinfo->gen >= 6); brw_set_default_access_mode(p, BRW_ALIGN_16); if (dispatch_width == 16 && !devinfo->supports_simd16_3src) { brw_set_default_exec_size(p, BRW_EXECUTE_8); @@ -1654,7 +1652,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case BRW_OPCODE_LRP: - assert(brw->gen >= 6); + assert(devinfo->gen >= 6); brw_set_default_access_mode(p, BRW_ALIGN_16); if (dispatch_width == 16 && !devinfo->supports_simd16_3src) { brw_set_default_exec_size(p, BRW_EXECUTE_8); @@ -1710,11 +1708,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) brw_SHL(p, dst, src[0], src[1]); break; case BRW_OPCODE_F32TO16: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); brw_F32TO16(p, dst, src[0]); break; case BRW_OPCODE_F16TO32: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); brw_F16TO32(p, dst, src[0]); break; case BRW_OPCODE_CMP: @@ -1729,7 +1727,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) * coissuing would affect CMP instructions not otherwise affected by * the errata. */ - if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) { + if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) { if (dst.file == BRW_GENERAL_REGISTER_FILE) { brw_set_default_exec_size(p, BRW_EXECUTE_8); brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); @@ -1760,32 +1758,32 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) brw_SEL(p, dst, src[0], src[1]); break; case BRW_OPCODE_BFREV: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); /* BFREV only supports UD type for src and dst. */ brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD), retype(src[0], BRW_REGISTER_TYPE_UD)); break; case BRW_OPCODE_FBH: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); /* FBH only supports UD type for dst. */ brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]); break; case BRW_OPCODE_FBL: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); /* FBL only supports UD type for dst. */ brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]); break; case BRW_OPCODE_CBIT: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); /* CBIT only supports UD type for dst. */ brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]); break; case BRW_OPCODE_ADDC: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); brw_ADDC(p, dst, src[0], src[1]); break; case BRW_OPCODE_SUBB: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); brw_SUBB(p, dst, src[0], src[1]); break; case BRW_OPCODE_MAC: @@ -1793,7 +1791,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case BRW_OPCODE_BFE: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); brw_set_default_access_mode(p, BRW_ALIGN_16); if (dispatch_width == 16 && !devinfo->supports_simd16_3src) { brw_set_default_exec_size(p, BRW_EXECUTE_8); @@ -1809,13 +1807,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case BRW_OPCODE_BFI1: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we * should * * "Force BFI instructions to be executed always in SIMD8." */ - if (dispatch_width == 16 && brw->is_haswell) { + if (dispatch_width == 16 && devinfo->is_haswell) { brw_set_default_exec_size(p, BRW_EXECUTE_8); brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1])); @@ -1827,7 +1825,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) } break; case BRW_OPCODE_BFI2: - assert(brw->gen >= 7); + assert(devinfo->gen >= 7); brw_set_default_access_mode(p, BRW_ALIGN_16); /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we * should @@ -1838,7 +1836,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) * do for the other three-source instructions. */ if (dispatch_width == 16 && - (brw->is_haswell || !devinfo->supports_simd16_3src)) { + (devinfo->is_haswell || !devinfo->supports_simd16_3src)) { brw_set_default_exec_size(p, BRW_EXECUTE_8); brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2])); @@ -1854,7 +1852,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case BRW_OPCODE_IF: if (inst->src[0].file != BAD_FILE) { /* The instruction has an embedded compare (only allowed on gen6) */ - assert(brw->gen == 6); + assert(devinfo->gen == 6); gen6_IF(p, inst->conditional_mod, src[0], src[1]); } else { brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8); @@ -1893,14 +1891,14 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case SHADER_OPCODE_LOG2: case SHADER_OPCODE_SIN: case SHADER_OPCODE_COS: - assert(brw->gen < 6 || inst->mlen == 0); + assert(devinfo->gen < 6 || inst->mlen == 0); assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); - if (brw->gen >= 7) { + if (devinfo->gen >= 7) { gen6_math(p, dst, brw_math_function(inst->opcode), src[0], brw_null_reg()); - } else if (brw->gen == 6) { + } else if (devinfo->gen == 6) { generate_math_gen6(inst, dst, src[0], brw_null_reg()); - } else if (brw->gen == 5 || brw->is_g4x) { + } else if (devinfo->gen == 5 || devinfo->is_g4x) { generate_math_g45(inst, dst, src[0]); } else { generate_math_gen4(inst, dst, src[0]); @@ -1909,11 +1907,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case SHADER_OPCODE_INT_QUOTIENT: case SHADER_OPCODE_INT_REMAINDER: case SHADER_OPCODE_POW: - assert(brw->gen < 6 || inst->mlen == 0); + assert(devinfo->gen < 6 || inst->mlen == 0); assert(inst->conditional_mod == BRW_CONDITIONAL_NONE); - if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) { + if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) { gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); - } else if (brw->gen >= 6) { + } else if (devinfo->gen >= 6) { generate_math_gen6(inst, dst, src[0], src[1]); } else { generate_math_gen4(inst, dst, src[0]); -- 2.30.2