From 5c06f150856af5ed9d0dd1f732f164c2040b6332 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 6 Sep 2020 13:08:57 +0100 Subject: [PATCH] add comments for DEC / TB --- src/soc/decoder/power_decoder2.py | 6 +++--- src/soc/simple/issuer.py | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 66cc8d97..e07a78e7 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -763,11 +763,11 @@ class PowerDecode2(Elaboratable): # check if instruction is privileged is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn) - # external interrupt? - with m.If(ext_irq & msr[MSR.EE]): + # external interrupt? only if MSR.EE set + with m.If(ext_irq & msr[MSR.EE]): # v3.0B p944 (MSR.EE) self.trap(m, TT.EINT, 0x500) - # decrement counter: TODO 32-bit version (MSR.LPCR) + # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR) with m.If(dec_spr[63] & msr[MSR.EE]): # v3.0B 6.5.11 p1076 self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065 diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 745f4a3d..91db8019 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -331,6 +331,8 @@ class TestIssuer(Elaboratable): DEC, TB, DEC, TB. note that SPR pipeline could have written a new value to DEC, however the regfile has "passthrough" on it so this *should* be ok. + + see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076 """ comb, sync = m.d.comb, m.d.sync -- 2.30.2