From 5c2ee2f1fe77697b7af9740f1d89c43a7c257bc5 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Mon, 12 Dec 2016 07:56:39 +0000 Subject: [PATCH] constraints.md (T): Use special memory constraint. * config/sparc/constraints.md (T): Use special memory constraint. (U): Minor tweak. (W): Add TARGET_ARCH64 test. * config/sparc/sparc.md (*movdi_insn_sp32): Replace 'W' with 'T'. (*movdf_insn_sp32): Likewise. (*mov_insn_sp32): Likewise. Replace 'e' with 'f' in conjunction with offsettable memory references. From-SVN: r243540 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/sparc/constraints.md | 15 ++++++++------- gcc/config/sparc/sparc.md | 12 ++++++------ 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d0d4001c0c4..bf789c6f2ca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-12-12 Eric Botcazou + + * config/sparc/constraints.md (T): Use special memory constraint. + (U): Minor tweak. + (W): Add TARGET_ARCH64 test. + * config/sparc/sparc.md (*movdi_insn_sp32): Replace 'W' with 'T'. + (*movdf_insn_sp32): Likewise. + (*mov_insn_sp32): Likewise. Replace 'e' with 'f' in + conjunction with offsettable memory references. + 2016-12-11 Sandra Loosemore * config/nios2/nios2.c (nios2_emit_move_sequence): Call copy_rtx diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md index 626ced79144..f0b69c23b5b 100644 --- a/gcc/config/sparc/constraints.md +++ b/gcc/config/sparc/constraints.md @@ -128,11 +128,11 @@ (and (match_code "const_double") (match_test "fp_high_losum_p (op)"))) -;; Not needed in 64-bit mode -(define_memory_constraint "T" +;; We need a special memory constraint because of the alignment requirement +(define_special_memory_constraint "T" "Memory reference whose address is aligned to 8-byte boundary" - (and (match_test "TARGET_ARCH32") - (match_code "mem") + (and (match_code "mem") + (match_test "TARGET_ARCH32") (match_test "memory_ok_for_ldd (op)"))) ;; This awkward register constraint is necessary because it is not @@ -174,16 +174,17 @@ ;; reg_class_for_constraint, and checks it against NO_REGS. (define_constraint "U" "Pseudo-register or hard even-numbered integer register" - (and (match_test "TARGET_ARCH32") - (match_code "reg") + (and (match_code "reg") (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER") (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0"))) + (match_test "TARGET_ARCH32") (match_test "register_ok_for_ldd (op)"))) -;; Equivalent to 'T' but available in 64-bit mode +;; Equivalent to 'T' but in 64-bit mode without alignment requirement (define_memory_constraint "W" "Memory reference for 'e' constraint floating-point register" (and (match_code "mem") + (match_test "TARGET_ARCH64") (match_test "memory_ok_for_ldd (op)"))) (define_memory_constraint "w" diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 767d50844df..d2a6da4941c 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1705,9 +1705,9 @@ (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,U,T,r,o,r,r,?*f,?T,?*f,?o,?*e,?*e, r,?*f,?*e,?W,*b,*b") + "=T,o,U,T,r,o,r,r,?*f,?T,?*f,?o,?*e,?*e, r,?*f,?*e,?T,*b,*b") (match_operand:DI 1 "input_operand" - " J,J,T,U,o,r,i,r, T,*f, o,*f, *e, *e,?*f, r, W,*e, J, P"))] + " J,J,T,U,o,r,i,r, T,*f, o,*f, *e, *e,?*f, r, T,*e, J, P"))] "TARGET_ARCH32 && (register_operand (operands[0], DImode) || register_or_zero_operand (operands[1], DImode))" @@ -2336,9 +2336,9 @@ (define_insn "*movdf_insn_sp32" [(set (match_operand:DF 0 "nonimmediate_operand" - "=T,o,b,b,e,e,*r, f, e,W,U,T, f,o, *r,*r, o") + "=T,o,b,b,e,e,*r, f, e,T,U,T, f,o, *r,*r, o") (match_operand:DF 1 "input_operand" - " G,G,G,C,e,e, f,*r,W#F,e,T,U,o#F,f,*rF, o,*r"))] + " G,G,G,C,e,e, f,*r,T#F,e,T,U,o#F,f,*rF, o,*r"))] "TARGET_ARCH32 && (register_operand (operands[0], DFmode) || register_or_zero_or_all_ones_operand (operands[1], DFmode))" @@ -8543,9 +8543,9 @@ (define_insn "*mov_insn_sp32" [(set (match_operand:VM64 0 "nonimmediate_operand" - "=T,o,e,e,e,*r, f,e,W,U,T,e,o,*r,*r, o") + "=T,o,e,e,e,*r, f,e,T,U,T,f,o,*r,*r, o") (match_operand:VM64 1 "input_operand" - " Y,Y,Y,Z,e, f,*r,W,e,T,U,o,e,*r, o,*r"))] + " Y,Y,Y,Z,e, f,*r,T,e,T,U,o,f,*r, o,*r"))] "TARGET_VIS && TARGET_ARCH32 && (register_operand (operands[0], mode) -- 2.30.2