From 5c450a7a4b6e49fa7715ffcbe6396b033c60734f Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 14 Sep 2022 19:25:19 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 8bc64c28f..296c8382d 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -181,11 +181,17 @@ the same space): (fits within svshape's XO encoding) * **svindex** - convenience instruction for setting up "Indexed" REMAP. -# SVP64 and SVP64-Single 24-bit Prefixes +# SVP64 24-bit Prefixes + +The SVP64 24-bit Prefix (RM) provides several options, +all fitting within the 24-bit space (and no other). +These Modes do not interact with SVSTATE per se. SVSTATE +primarily controls the looping (quantity, order), RM +influences the *elements* (the Suffix). There is however +some close interaction when it comes to predication. +REMAP is separately +outlined in another section. -The SVP64 24-bit Prefix provides several options, -all fitting within the 24-bit space (and no other). REMAP is separately -outlined below. The primary options all of which are aimed at reducing instruction count and reducing assembler complexity are: @@ -197,7 +203,12 @@ count and reducing assembler complexity are: between all formats. * predication. this is an absolutely essential feature for a 3D GPU VPU ISA. CR Fields are available as Predicate Masks hence the reason for their - extension to 128. + extension to 128. Twin-Predication is also provided: this may best + be envisaged as back-to-back VGATHER-VSCATTER but is not restricted + to LD/ST, its use saves on instruction count. Enabling one or other + of the predicates provides all of the other types of operations + found in Vector ISAs (VEXTRACT, VINSERT etc) again with no need + to actually provide explicit such instructions. * Saturation. **all** LD/ST and Arithmetic and Logical operations may be saturated (without adding explicit scalar saturated opcodes) * Reduction and Prefix-Sum (Fibonnacci Series) Modes -- 2.30.2