From 5c56e93a3097688bb92e76f9b462d35d04da39a3 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Wed, 19 Oct 2022 23:23:29 +0300 Subject: [PATCH] sv_binutils_fptrans: fix registers generation --- src/openpower/sv/sv_binutils_fptrans.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/openpower/sv/sv_binutils_fptrans.py b/src/openpower/sv/sv_binutils_fptrans.py index d0e83460..d6aec3af 100644 --- a/src/openpower/sv/sv_binutils_fptrans.py +++ b/src/openpower/sv/sv_binutils_fptrans.py @@ -139,12 +139,16 @@ def asm(entry, binutils=False, regex=False): for (idx, operand) in enumerate(operands): values = [] for each in operands: - if binutils and each.name in ("RT", "RA", "RB"): + if binutils and each.name in ("FRT", "FRA", "FRB"): + values.append("f0") + elif binutils and each.name in ("RT", "RA", "RB"): values.append("r0") else: values.append("0") value = str((1 << len(operand.span)) - 1) - if binutils and operand.name in ("RT", "RA", "RB"): + if binutils and operand.name in ("FRT", "FRA", "FRB"): + value = f"f{value}" + elif binutils and operand.name in ("RT", "RA", "RB"): value = f"r{value}" values[idx] = value sep = "\s+" if regex else " " -- 2.30.2