From 5c7cab896aac6ddb0bf33f60fd790e4d31c6f399 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 25 Jul 2018 15:58:24 +0100
Subject: [PATCH]

---
 shakti/m_class/AXI.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index bb1827f51..c2be19648 100644
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -4,3 +4,4 @@ See also [[wishbone]] Bus
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
 * <https://github.com/alexforencich/verilog-axis>
+* https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl
-- 
2.30.2