From 5c8fe481c2051899c10d7b731f8a6de9fa6a5282 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 31 Jul 2019 20:38:13 +0100 Subject: [PATCH] move FPAddStage0Data to separate module --- src/ieee754/fpadd/add0.py | 26 +++++--------------------- src/ieee754/fpadd/datastruct.py | 26 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 21 deletions(-) create mode 100644 src/ieee754/fpadd/datastruct.py diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py index fd908879..e5845b44 100644 --- a/src/ieee754/fpadd/add0.py +++ b/src/ieee754/fpadd/add0.py @@ -9,25 +9,9 @@ from nmigen.cli import main, verilog from nmutil.pipemodbase import PipeModBase -from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord from ieee754.fpcommon.denorm import FPSCData from ieee754.fpcommon.getop import FPPipeContext - - -class FPAddStage0Data: - - def __init__(self, pspec): - width = pspec.width - self.z = FPNumBaseRecord(width, False) - self.out_do_z = Signal(reset_less=True) - self.oz = Signal(width, reset_less=True) - self.tot = Signal(self.z.m_width + 4, reset_less=True) # 4 extra bits - self.ctx = FPPipeContext(pspec) - self.muxid = self.ctx.muxid - - def eq(self, i): - return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), - self.tot.eq(i.tot), self.ctx.eq(i.ctx)] +from ieee754.fpadd.datastruct import FPAddStage0Data class FPAddStage0Mod(PipeModBase): @@ -51,10 +35,10 @@ class FPAddStage0Mod(PipeModBase): am0 = Signal(len(self.i.a.m)+1, reset_less=True) bm0 = Signal(len(self.i.b.m)+1, reset_less=True) comb += [seq.eq(self.i.a.s == self.i.b.s), - mge.eq(self.i.a.m >= self.i.b.m), - am0.eq(Cat(self.i.a.m, 0)), - bm0.eq(Cat(self.i.b.m, 0)) - ] + mge.eq(self.i.a.m >= self.i.b.m), + am0.eq(Cat(self.i.a.m, 0)), + bm0.eq(Cat(self.i.b.m, 0)) + ] # same-sign (both negative or both positive) add mantissas with m.If(~self.i.out_do_z): diff --git a/src/ieee754/fpadd/datastruct.py b/src/ieee754/fpadd/datastruct.py new file mode 100644 index 00000000..e2ca9427 --- /dev/null +++ b/src/ieee754/fpadd/datastruct.py @@ -0,0 +1,26 @@ +"""IEEE754 Floating Point Adder Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton + +""" + +from nmigen import Module, Signal + +from ieee754.fpcommon.fpbase import FPNumBaseRecord +from ieee754.fpcommon.getop import FPPipeContext + + +class FPAddStage0Data: + + def __init__(self, pspec): + width = pspec.width + self.z = FPNumBaseRecord(width, False) + self.out_do_z = Signal(reset_less=True) + self.oz = Signal(width, reset_less=True) + self.tot = Signal(self.z.m_width + 4, reset_less=True) # 4 extra bits + self.ctx = FPPipeContext(pspec) + self.muxid = self.ctx.muxid + + def eq(self, i): + return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), + self.tot.eq(i.tot), self.ctx.eq(i.ctx)] -- 2.30.2