From 5cbc5bc1998dce20753d2d66b428630dbda0b956 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Fri, 26 Apr 2019 17:13:28 -0500
Subject: [PATCH] Adding testing of cpu variants.

---
 litex/soc/integration/soc_core.py |  6 ++--
 test/test_targets.py              | 60 ++++++++++++++++++++++++++++---
 2 files changed, 58 insertions(+), 8 deletions(-)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index c5fe7ad2..a36b68a2 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -54,7 +54,7 @@ Invalid extension in cpu_variant value: {}
 
 Possible Values:
 """.format(variant)
-        for e in CPU_VARIANTS_EXTENSIONS.items():
+        for e in CPU_VARIANTS_EXTENSIONS:
             msg += " - {}\n".format(e)
         ValueError.__init__(self, msg)
 
@@ -217,8 +217,8 @@ class SoCCore(Module):
 
         # Check for valid CPU extensions.
         for ext in sorted(cpu_variant_ext):
-            if cpu_variant_ext not in CPU_VARIANTS_EXTENSIONS:
-                raise InvalidCPUExtension(cpu_variant)
+            if ext not in CPU_VARIANTS_EXTENSIONS:
+                raise InvalidCPUExtensionError(cpu_variant)
             self.cpu_variant += "+"+ext
 
         if integrated_rom_size:
diff --git a/test/test_targets.py b/test/test_targets.py
index 1b015137..eadbd8e6 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -1,3 +1,4 @@
+import subprocess
 import unittest
 import os
 
@@ -6,6 +7,9 @@ from migen import *
 from litex.soc.integration.builder import *
 
 
+RUNNING_ON_TRAVIS = (os.getenv('TRAVIS', 'false').lower() == 'true')
+
+
 def build_test(socs):
     errors = 0
     for soc in socs:
@@ -98,8 +102,54 @@ class TestTargets(unittest.TestCase):
         platforms += ["avalanche"]                                 # PolarFire
 
         for p in platforms:
-            os.system("litex/boards/targets/simple.py litex.boards.platforms." + p +
-                " --cpu-type=vexriscv " +
-                " --no-compile-software " +
-                " --no-compile-gateware " +
-                " --uart-stub=True")
+            with self.subTest(platform=p):
+                cmd = """\
+litex/boards/targets/simple.py litex.boards.platforms.{p} \
+    --cpu-type=vexriscv     \
+    --no-compile-software   \
+    --no-compile-gateware   \
+    --uart-stub=True        \
+""".format(p=p)
+                subprocess.check_call(cmd, shell=True)
+
+    def run_variants(self, cpu, variants):
+        for v in variants:
+            with self.subTest(cpu=cpu, variant=v):
+                self.run_variant(cpu, v)
+
+    def run_variant(self, cpu, variant):
+        cmd = """\
+litex/boards/targets/simple.py litex.boards.platforms.arty \
+    --cpu-type={c}          \
+    --cpu-variant={v}       \
+    --no-compile-software   \
+    --no-compile-gateware   \
+    --uart-stub=True        \
+""".format(c=cpu, v=variant)
+        subprocess.check_output(cmd, shell=True)
+
+    # Build some variants for the arty platform to make sure they work.
+    def test_variants_riscv(self):
+        cpu_variants = {
+            'picorv32': ('standard', 'minimal'),
+            'vexriscv': ('standard', 'minimal', 'lite', 'lite+debug', 'full+debug'),
+            'minerva': ('standard',),
+        }
+        for cpu, variants in cpu_variants.items():
+            self.run_variants(cpu, variants)
+
+    def test_bad_variants(self):
+        with self.assertRaises(subprocess.CalledProcessError):
+            self.run_variant('vexriscv', 'bad')
+
+    def test_bad_variant_extension(self):
+        with self.assertRaises(subprocess.CalledProcessError):
+            self.run_variant('vexriscv', 'standard+bad')
+
+    @unittest.skipIf(RUNNING_ON_TRAVIS, "No lm32 toolchain on Travis-CI")
+    def test_variants_lm32(self):
+        self.run_variants('lm32', ('standard', 'minimal', 'lite'))
+
+    @unittest.skipIf(RUNNING_ON_TRAVIS, "No or1k toolchain on Travis-CI")
+    def test_variants_or1k(self):
+        self.run_variants('or1k', ('standard', 'linux'))
-- 
2.30.2