From 5cc7636993ca50dd8a602ee5a4fef0f4fbf29cd2 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 30 Aug 2019 17:19:46 -0700 Subject: [PATCH] iris: Enable Gen11 Color/Z write merging optimization TCCNTLREG contains additional L3 cache write merging optimizations. The default value on my system appears to be: - URB Partial Write Merging (bit 0) - L3 Data Partial Write Merging (bit 2) - TC Disable (bit 3) Windows drivers appear to set bit 1 as well to enable "Color/Z Partial Write Merging". This should solve an issue we were seeing where MRT benchmarks were using substantially more bandwidth than they ought. However, we have not observed it to cause measurable FPS gains. It is unclear whether we should be setting bit 0 or bit 3, so for now we leave those at the hardware default value. Improves performance in Manhattan 3.0 by 6% on ICL 8x8 at a fixed frequency, according to Felix Degrood. I didn't see any improvements at out-of-the-box power management settings, however. Acked-by: Jason Ekstrand --- src/gallium/drivers/iris/iris_state.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 3e0bedddfd7..6e90d33502b 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -931,6 +931,14 @@ iris_init_render_context(struct iris_batch *batch) #endif #if GEN_GEN == 11 + iris_pack_state(GENX(TCCNTLREG), ®_val, reg) { + reg.L3DataPartialWriteMergingEnable = true; + reg.ColorZPartialWriteMergingEnable = true; + reg.URBPartialWriteMergingEnable = true; + reg.TCDisable = true; + } + iris_emit_lri(batch, TCCNTLREG, reg_val); + iris_pack_state(GENX(SAMPLER_MODE), ®_val, reg) { reg.HeaderlessMessageforPreemptableContexts = 1; reg.HeaderlessMessageforPreemptableContextsMask = 1; -- 2.30.2