From 5d2dba78c962b0b854b62868a7c36b35cf328d5c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 Oct 2021 17:04:20 +0100 Subject: [PATCH] work pack table --- SEP-210803722-Libre-SOC-8-core.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/SEP-210803722-Libre-SOC-8-core.mdwn b/SEP-210803722-Libre-SOC-8-core.mdwn index 9703c89cb..c69deae53 100644 --- a/SEP-210803722-Libre-SOC-8-core.mdwn +++ b/SEP-210803722-Libre-SOC-8-core.mdwn @@ -419,6 +419,7 @@ Table 3.1b(1) |Work Package Number |1 | +| ---- | -------- | |Lead beneficiary |NLnet | |Title |NLnet mini-grants | |Participant Number |5 | @@ -468,6 +469,7 @@ Table 3.1b(2) |Work Package Number |2 | +| ---- | -------- | |Lead beneficiary |Libre-SOC | |Title |SVP64 Standards, RFC submission to OPF ISA WG | |Participant Number |2 | @@ -514,6 +516,7 @@ Table 3.1b(3) |Work Package Number |3 | +| ---- | -------- | |Lead beneficiary |Libre-SOC | |Title |Power ISA Simulator and Compliance Test Suite | |Participant Number |2 |1 | @@ -556,6 +559,7 @@ Deliverables: Table 3.1b(4) |Work Package Number |4 | +| ---- | -------- | |Lead beneficiary |RED Semiconductor Ltd | |Title |Compilers and Software Libraries | |Participant Number |1 |2 | @@ -598,6 +602,7 @@ Table 3.1b(5) |Work Package Number |5 | +| ---- | -------- | |Lead beneficiary |Libre-SOC | |Title |Enhancement of Libre-SOC HDL | |Participant Number |2 |1 |3 | @@ -646,6 +651,7 @@ Table 3.1b(6) |Work Package Number |6 | +| ---- | -------- | |Lead beneficiary |CNRS | |Title |EMF Signature Hardware security | |Participant Number |3 |4 |2 |1 | @@ -691,6 +697,7 @@ Table 3.1b(7) |Work Package Number |7 | +| ---- | -------- | |Lead beneficiary |Libre-SOC | |Title |Cell Libraries for smaller geometries | |Participant Number |3 |2 |1 | @@ -739,6 +746,7 @@ Table 3.1b(8) |Work Package Number |8 | +| ---- | -------- | |Lead beneficiary |Sorbonne Université (LIP6 Lab) | |Title |Improve Coriolis2 for smaller geometries | |Participant Number |3 |2 |1 | @@ -810,6 +818,7 @@ Table 3.1b(9) |Work Package Number |9 | +| ---- | -------- | |Lead beneficiary |Sorbonne Université (LIP6 Lab) | |Title |VLSI Layout, Tape-outs and ASIC testing | |Participant Number |3 |2 |1 | @@ -856,6 +865,7 @@ Table 3.1b(10) |Work Package Number |10 | +| ---- | -------- | |Lead beneficiary |RED | |Title |VLSI Layout, Tape-outs and ASIC testing | |Participant Number |1 |3 |2 |5 | @@ -893,6 +903,7 @@ Table 3.1b(11) |Work Package Number |11 | +| ---- | -------- | |Lead beneficiary |HELIX | |Title | | |Participant Number |1 |6 | | -- 2.30.2