From 5d331251cfbc304982517c60a854706fa6b60f71 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Tue, 3 Sep 2019 16:30:14 -0700 Subject: [PATCH] iris: Prepare resources before stencil blit operation We have to resolve destination surfaces if we are bliting to and from the same surface. v2: Revert unrelated change (Nanley Chery) Signed-off-by: Sagar Ghuge Reviewed-by: Nanley Chery --- src/gallium/drivers/iris/iris_blit.c | 59 ++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index 9c1a8dbe892..e10e54667f4 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -479,16 +479,54 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) } } + struct iris_resource *stc_dst = NULL; + enum isl_aux_usage stc_src_aux_usage, stc_dst_aux_usage; if ((info->mask & PIPE_MASK_S) && util_format_has_stencil(util_format_description(info->dst.format)) && util_format_has_stencil(util_format_description(info->src.format))) { - struct iris_resource *src_res, *dst_res, *junk; + struct iris_resource *src_res, *junk; + struct blorp_surf src_surf, dst_surf; iris_get_depth_stencil_resources(info->src.resource, &junk, &src_res); - iris_get_depth_stencil_resources(info->dst.resource, &junk, &dst_res); + iris_get_depth_stencil_resources(info->dst.resource, &junk, &stc_dst); + + struct iris_format_info src_fmt = + iris_format_for_usage(devinfo, src_res->base.format, + ISL_SURF_USAGE_TEXTURE_BIT); + stc_src_aux_usage = + iris_resource_texture_aux_usage(ice, src_res, src_fmt.fmt, 0); + + struct iris_format_info dst_fmt = + iris_format_for_usage(devinfo, stc_dst->base.format, + ISL_SURF_USAGE_RENDER_TARGET_BIT); + stc_dst_aux_usage = + iris_resource_render_aux_usage(ice, stc_dst, dst_fmt.fmt, false, false); + + /* Resolve destination surface before blit because : + * 1. when we try to blit from the same surface, we can't read and + * write to the same surfaces at the same time when we have + * compression enabled so it's safe to resolve surface first and then + * do blit. + * 2. While bliting from one surface to another surface, we might be + * mixing compression formats, Our experiments shows that if after + * blit if we set DepthStencilResource flag to 0, blit passes but + * clear fails. + * + * XXX: In second case by destructing the compression, we might lose + * some performance. + */ + if (devinfo->gen >= 12) + stc_dst_aux_usage = ISL_AUX_USAGE_NONE; + + iris_resource_prepare_access(ice, batch, src_res, info->src.level, 1, + info->src.box.z, info->src.box.depth, + stc_src_aux_usage, false); + iris_resource_prepare_access(ice, batch, stc_dst, info->dst.level, 1, + info->dst.box.z, info->dst.box.depth, + stc_dst_aux_usage, false); iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, &src_res->base, - ISL_AUX_USAGE_NONE, info->src.level, false); - iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, &dst_res->base, - ISL_AUX_USAGE_NONE, info->dst.level, true); + stc_src_aux_usage, info->src.level, false); + iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, &stc_dst->base, + stc_dst_aux_usage, info->dst.level, true); for (int slice = 0; slice < info->dst.box.depth; slice++) { iris_batch_maybe_flush(batch, 1500); @@ -508,8 +546,15 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) tex_cache_flush_hack(batch, src_fmt.fmt, src_res->surf.format); - iris_resource_finish_write(ice, dst_res, info->dst.level, info->dst.box.z, - info->dst.box.depth, dst_aux_usage); + if (info->mask & main_mask) { + iris_resource_finish_write(ice, dst_res, info->dst.level, info->dst.box.z, + info->dst.box.depth, dst_aux_usage); + } + + if (stc_dst) { + iris_resource_finish_write(ice, stc_dst, info->dst.level, info->dst.box.z, + info->dst.box.depth, stc_dst_aux_usage); + } iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *) info->dst.resource, -- 2.30.2