From 5d34a9975f47e8cd4f57c304f5e39ab6c7201603 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Tue, 29 May 2018 17:10:47 -0700 Subject: [PATCH] intel: Update alignment restrictions for HiZ surfaces. v2 (Nanley): * Maintain a chronological ordering for HiZ alignments. Suggested by Ken. Co-authored-by: Nanley Chery Reviewed-by: Kenneth Graunke --- src/intel/isl/isl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 5fd6aded2ae..f1859588013 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -656,11 +656,17 @@ isl_choose_image_alignment_el(const struct isl_device *dev, if (ISL_DEV_GEN(dev) == 6) { /* HiZ surfaces on Sandy Bridge are packed tightly. */ *image_align_el = isl_extent3d(1, 1, 1); - } else { + } else if (ISL_DEV_GEN(dev) < 12) { /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the * primary surface which works out to 2x2 HiZ elments. */ *image_align_el = isl_extent3d(2, 2, 1); + } else { + /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the + * primary surface which works out to 2x4 HiZ elments. + * TODO: Verify + */ + *image_align_el = isl_extent3d(2, 4, 1); } return; } -- 2.30.2