From 5d3ae76af134ab1f901f05223e57fc4ef951b18c Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Fri, 19 May 2017 13:29:21 +0200 Subject: [PATCH] rs6000: Make constant formation a tiny bit better If we cannot load a constant into a register in one insn, and that constant is a valid mask (for rotate instructions), we currently prefer to load -1 and then mask it. This patch makes us not do that if instead we could use two add or or instructions, since those are sometimes faster on certain CPUs (and never are slower). * config/rs6000/rs6000.md (splitter to load of -1 and mask): Don't use this splitter if two add or or instructions would also work for the constant we want to generate. From-SVN: r248265 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.md | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9e386f75933..9006383293e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-05-19 Segher Boessenkool + + * config/rs6000/rs6000.md (splitter to load of -1 and mask): Don't + use this splitter if two add or or instructions would also work for + the constant we want to generate. + 2017-05-19 Richard Biener PR build/80821 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 26baaaf1524..799d786edfe 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8732,6 +8732,7 @@ (match_operand:DI 1 "const_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1 + && !IN_RANGE (INTVAL (operands[1]), -0x80000000, 0xffffffff) && rs6000_is_valid_and_mask (operands[1], DImode)" [(set (match_dup 0) (const_int -1)) -- 2.30.2