From 5d443b20afd32d4d82d0285290f39ebdb061cda9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 04:19:19 +0100 Subject: [PATCH] add stub for SV REG configs --- riscv/processor.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 83c6439..71b030b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -346,6 +346,15 @@ void processor_t::set_csr(int which, reg_t val) state.vl = std::min(state.mvl, state.XPR[val]); state.XPR.write(val, state.vl); break; + case CSR_SVREGCFG0: + case CSR_SVREGCFG1: + case CSR_SVREGCFG2: + case CSR_SVREGCFG3: + case CSR_SVREGCFG4: + case CSR_SVREGCFG5: + case CSR_SVREGCFG6: + case CSR_SVREGCFG7: + break; #endif case CSR_FFLAGS: dirty_fp_state; -- 2.30.2