From 5d5b92046e87d26ecce32d90c4460316787e27d0 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 12 Dec 2020 19:02:31 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64/discussion.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn index b1d09d620..a400cbd49 100644 --- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn +++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn @@ -12,9 +12,9 @@ do not try to jam VL or MAXVL in. go with the flow of 24 bits spare. * 1: select INT or CR predication * 3: predicate selection and inversion (QTY 2 for tpred) * 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg -* 3: saturate mode +* 5: mode -totals: 22 bits (dest elwidth shared) +totals: 24 bits (dest elwidth shared) http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html -- 2.30.2