From 5d610025102706238418712664d6db4085f00437 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 3 Apr 2022 11:23:46 +0100 Subject: [PATCH] redo start address of firmware so it can be specified -DBOOT_INIT_BASE --- README.txt | 5 ++++ coldboot/Makefile | 15 ++++++++--- coldboot/coldboot.c | 35 ++++++++++++++++++------- coldboot/{powerpc.lds => powerpc.lds.S} | 2 +- src/ls2.py | 3 +-- 5 files changed, 45 insertions(+), 15 deletions(-) rename coldboot/{powerpc.lds => powerpc.lds.S} (95%) diff --git a/README.txt b/README.txt index 0bd83af..bedf8c5 100644 --- a/README.txt +++ b/README.txt @@ -1,3 +1,8 @@ python3 src/ls2.py versa_ecp5 ./hello_world/hello_world.bin openocd -f top-openocd.cfg \ -c "transport select jtag; init; svf -quiet top.svf; exit" + +# Versa ECP5 ecpprog QSPI + +ecpprog -o 0 binary.bin + diff --git a/coldboot/Makefile b/coldboot/Makefile index 01ec008..b1bd8de 100644 --- a/coldboot/Makefile +++ b/coldboot/Makefile @@ -12,6 +12,11 @@ SHORT_TIMER_MULT = 100 #LONG_TIMER_MULT = 1 #SHORT_TIMER_MULT = 1 +# SPI boot address 0x1000_0000, main SRAM boot would be 0x0000_0000 +# but remember to recompile external_core_top.v with a matching +# --pc_reset=0xNNNNNNNN +BOOT_INIT_BASE ?= 0x10000000 + LIBGRAMDIR = ../libgram LIBGRAMINC = ../libgram/include @@ -29,6 +34,7 @@ CFLAGS = -Os -g -Wall -std=c99 -msoft-float -mno-string \ -fdata-sections -ffunction-sections -I../include \ -I $(LIBGRAMINC) \ -DLONG_TIMER_MULT=$(LONG_TIMER_MULT) \ + -DBOOT_INIT_BASE=$(BOOT_INIT_BASE) \ -DSHORT_TIMER_MULT=$(SHORT_TIMER_MULT) ASFLAGS = $(CFLAGS) LDFLAGS = -T powerpc.lds @@ -47,8 +53,11 @@ dfii.o: ../libgram/src/dfii.c calibration.o: ../libgram/src/calibration.c $(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ -coldboot.elf: coldboot.o head.o ../lib/console.o $(GRAMOBJS) - $(LD) $(LDFLAGS) -o $@ $^ +powerpc.lds: powerpc.lds.S + $(CC) $(CFLAGS) -P -E powerpc.lds.S -o powerpc.lds + +coldboot.elf: coldboot.o head.o ../lib/console.o $(GRAMOBJS) powerpc.lds + $(LD) $(LDFLAGS) -o $@ coldboot.o head.o ../lib/console.o $(GRAMOBJS) coldboot.bin: coldboot.elf $(OBJCOPY) -O binary $^ $@ @@ -59,7 +68,7 @@ coldboot.hex: coldboot.bin clean: - @rm -f *.o coldboot.elf coldboot.bin coldboot.hex coldboot.as + @rm -f *.o coldboot.elf coldboot.bin coldboot.hex coldboot.as powerpc.lds distclean: clean rm -f *~ diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c index dcf6277..90a5698 100644 --- a/coldboot/coldboot.c +++ b/coldboot/coldboot.c @@ -67,23 +67,40 @@ int main(void) { //puts("Firmware launched...\n"); puts("fw.."); -#if 1 #if 1 // print out configuration parameters for QSPI volatile uint32_t *qspi_cfg = (uint32_t*)0xc0003000; - for (int k=0; k < 2; k++) { + for (int k=0; k < 10; k++) { tmp = readl((unsigned long)&(qspi_cfg[k])); - //puts("cfg"); - //uart_writeuint32(k); - //puts(" "); - //uart_writeuint32(tmp); - //puts("\n"); + puts("cfg"); + uart_writeuint32(k); + puts(" "); + uart_writeuint32(tmp); + puts("\n"); } -#endif + volatile uint32_t *qspi = (uint32_t*)0x10000000; + volatile uint8_t *qspi_bytes = (uint8_t*)0x10000000; // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0])); // tmp = readl((unsigned long)&(qspi[0])); -#if 1 +for (i=0;i<1000;i++) { + writel(0xDEAF0123+i, (unsigned long)&(qspi[i])); +} +for (i=0;i<1000;i++) { + if (i%8 == 0) puts("\r\n"); + tmp = readl((unsigned long)&(qspi[i])); + uart_writeuint32(tmp); + puts(" "); +} +putchar(10); +putchar(10); +for (i=0;i<1000;i++) { + if (i%8 == 0) puts("\r\n"); + tmp = readb((unsigned long)&(qspi_bytes[i])); + uart_writeuint32(tmp); + puts(" "); +} +#if 0 while (1) { // quick read tmp = readl((unsigned long)&(qspi[0x1000/4])); diff --git a/coldboot/powerpc.lds b/coldboot/powerpc.lds.S similarity index 95% rename from coldboot/powerpc.lds rename to coldboot/powerpc.lds.S index 00aba33..b673295 100644 --- a/coldboot/powerpc.lds +++ b/coldboot/powerpc.lds.S @@ -1,6 +1,6 @@ SECTIONS { - . = 0; + . = BOOT_INIT_BASE; _start = .; .head : { KEEP(*(.head)) diff --git a/src/ls2.py b/src/ls2.py index 1956a81..2284a04 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -686,8 +686,7 @@ def build_platform(fpga, firmware): Resource("spi_0", 0, Subsignal("dq", Pins("W2 V2 Y2 W1", dir="io")), Subsignal("cs_n", Pins("R2", dir="o")), - Attrs(PULLMODE="NONE", DRIVE="8", SLEWRATE="FAST", - IO_TYPE="LVCMOS33")) + Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33")) ] platform.add_resources(spi_0_ios) spi_0_pins = platform.request("spi_0", 0, dir={"dq":"io", "cs_n":"o"}, -- 2.30.2