From 5da10704bbd1e2f76180023be7e6b08ecc2d4a6a Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 22 Oct 2019 10:28:04 -0700 Subject: [PATCH] freedreno/ir3: use SSA flag on dest register too We did this in some places before, but not consistantly. But it will be useful for two-pass RA, to identify which registers have already been assigned. While we are cleaning this up, use __ssa_src() and new __ssa_dst() helper more consistently. (If nothing else, this reduces the # of callers of ir3_reg_create() to audit that we didn't miss something) Signed-off-by: Rob Clark --- src/freedreno/ir3/ir3.h | 62 ++++++++++++++-------------- src/freedreno/ir3/ir3_compiler_nir.c | 13 +++--- src/freedreno/ir3/ir3_context.c | 12 +++--- src/freedreno/ir3/ir3_group.c | 6 +-- 4 files changed, 48 insertions(+), 45 deletions(-) diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index 436feca2374..4f6e0478824 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -1103,6 +1103,26 @@ void ir3_legalize(struct ir3 *ir, bool *has_ssbo, bool *need_pixlod, int *max_ba /* ************************************************************************* */ /* instruction helpers */ +/* creates SSA src of correct type (ie. half vs full precision) */ +static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr, + struct ir3_instruction *src, unsigned flags) +{ + struct ir3_register *reg; + if (src->regs[0]->flags & IR3_REG_HALF) + flags |= IR3_REG_HALF; + reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags); + reg->instr = src; + reg->wrmask = src->regs[0]->wrmask; + return reg; +} + +static inline struct ir3_register * __ssa_dst(struct ir3_instruction *instr) +{ + struct ir3_register *reg = ir3_reg_create(instr, 0, 0); + reg->flags |= IR3_REG_SSA; + return reg; +} + static inline struct ir3_instruction * create_immed_typed(struct ir3_block *block, uint32_t val, type_t type) { @@ -1112,7 +1132,7 @@ create_immed_typed(struct ir3_block *block, uint32_t val, type_t type) mov = ir3_instr_create(block, OPC_MOV); mov->cat1.src_type = type; mov->cat1.dst_type = type; - ir3_reg_create(mov, 0, flags); + __ssa_dst(mov)->flags |= flags; ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val; return mov; @@ -1133,7 +1153,7 @@ create_uniform_typed(struct ir3_block *block, unsigned n, type_t type) mov = ir3_instr_create(block, OPC_MOV); mov->cat1.src_type = type; mov->cat1.dst_type = type; - ir3_reg_create(mov, 0, flags); + __ssa_dst(mov)->flags |= flags; ir3_reg_create(mov, n, IR3_REG_CONST | flags); return mov; @@ -1154,7 +1174,7 @@ create_uniform_indirect(struct ir3_block *block, int n, mov = ir3_instr_create(block, OPC_MOV); mov->cat1.src_type = TYPE_U32; mov->cat1.dst_type = TYPE_U32; - ir3_reg_create(mov, 0, 0); + __ssa_dst(mov); ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n; ir3_instr_set_address(mov, address); @@ -1162,24 +1182,11 @@ create_uniform_indirect(struct ir3_block *block, int n, return mov; } -/* creates SSA src of correct type (ie. half vs full precision) */ -static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr, - struct ir3_instruction *src, unsigned flags) -{ - struct ir3_register *reg; - if (src->regs[0]->flags & IR3_REG_HALF) - flags |= IR3_REG_HALF; - reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags); - reg->instr = src; - reg->wrmask = src->regs[0]->wrmask; - return reg; -} - static inline struct ir3_instruction * ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type) { struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV); - ir3_reg_create(instr, 0, 0); /* dst */ + __ssa_dst(instr); if (src->regs[0]->flags & IR3_REG_ARRAY) { struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY); src_reg->array = src->regs[0]->array; @@ -1202,7 +1209,7 @@ ir3_COV(struct ir3_block *block, struct ir3_instruction *src, debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags); - ir3_reg_create(instr, 0, dst_flags); /* dst */ + __ssa_dst(instr)->flags |= dst_flags; __ssa_src(instr, src, 0); instr->cat1.src_type = src_type; instr->cat1.dst_type = dst_type; @@ -1237,7 +1244,7 @@ ir3_##name(struct ir3_block *block, \ { \ struct ir3_instruction *instr = \ ir3_instr_create(block, opc); \ - ir3_reg_create(instr, 0, 0); /* dst */ \ + __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ instr->flags |= flag; \ return instr; \ @@ -1253,7 +1260,7 @@ ir3_##name(struct ir3_block *block, \ { \ struct ir3_instruction *instr = \ ir3_instr_create(block, opc); \ - ir3_reg_create(instr, 0, 0); /* dst */ \ + __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ __ssa_src(instr, b, bflags); \ instr->flags |= flag; \ @@ -1271,7 +1278,7 @@ ir3_##name(struct ir3_block *block, \ { \ struct ir3_instruction *instr = \ ir3_instr_create2(block, opc, 4); \ - ir3_reg_create(instr, 0, 0); /* dst */ \ + __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ __ssa_src(instr, b, bflags); \ __ssa_src(instr, c, cflags); \ @@ -1291,7 +1298,7 @@ ir3_##name(struct ir3_block *block, \ { \ struct ir3_instruction *instr = \ ir3_instr_create2(block, opc, 5); \ - ir3_reg_create(instr, 0, 0); /* dst */ \ + __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ __ssa_src(instr, b, bflags); \ __ssa_src(instr, c, cflags); \ @@ -1400,21 +1407,16 @@ ir3_SAM(struct ir3_block *block, opc_t opc, type_t type, struct ir3_instruction *src0, struct ir3_instruction *src1) { struct ir3_instruction *sam; - struct ir3_register *reg; sam = ir3_instr_create(block, opc); sam->flags |= flags | IR3_INSTR_S2EN; - ir3_reg_create(sam, 0, 0)->wrmask = wrmask; + __ssa_dst(sam)->wrmask = wrmask; __ssa_src(sam, samp_tex, IR3_REG_HALF); if (src0) { - reg = ir3_reg_create(sam, 0, IR3_REG_SSA); - reg->wrmask = (1 << (src0->regs_count - 1)) - 1; - reg->instr = src0; + __ssa_src(sam, src0, 0)->wrmask = (1 << (src0->regs_count - 1)) - 1; } if (src1) { - reg = ir3_reg_create(sam, 0, IR3_REG_SSA); - reg->instr = src1; - reg->wrmask = (1 << (src1->regs_count - 1)) - 1; + __ssa_src(sam, src1, 0)->wrmask =(1 << (src1->regs_count - 1)) - 1; } sam->cat5.type = type; diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index b827a4bef6e..1bc89819dfb 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -51,9 +51,8 @@ create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n, mov = ir3_instr_create(block, OPC_MOV); mov->cat1.src_type = TYPE_U32; mov->cat1.dst_type = TYPE_U32; - ir3_reg_create(mov, 0, 0); - src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV); - src->instr = collect; + __ssa_dst(mov); + src = __ssa_src(mov, collect, IR3_REG_RELATIV); src->size = arrsz; src->array.offset = n; @@ -69,9 +68,7 @@ create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask) in = ir3_instr_create(ctx->in_block, OPC_META_INPUT); in->input.sysval = ~0; - ir3_reg_create(in, n, 0); - - in->regs[0]->wrmask = compmask; + __ssa_dst(in)->wrmask = compmask; return in; } @@ -1762,6 +1759,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) /* condition always goes in predicate register: */ cond->regs[0]->num = regid(REG_P0, 0); + cond->regs[0]->flags &= ~IR3_REG_SSA; kill = ir3_KILL(b, cond, 0); array_insert(ctx->ir, ctx->ir->predicates, kill); @@ -2191,7 +2189,7 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex) compile_assert(ctx, tex->src[idx].src.is_ssa); sam = ir3_META_TEX_PREFETCH(b); - ir3_reg_create(sam, 0, 0)->wrmask = MASK(ncomp); /* dst */ + __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */ sam->prefetch.input_offset = ir3_nir_coord_offset(tex->src[idx].src.ssa); sam->prefetch.tex = tex->texture_index; @@ -2550,6 +2548,7 @@ emit_stream_out(struct ir3_context *ctx) /* setup 'if (vtxcnt < maxvtxcnt)' condition: */ cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0); cond->regs[0]->num = regid(REG_P0, 0); + cond->regs[0]->flags &= ~IR3_REG_SSA; cond->cat2.condition = IR3_COND_LT; /* condition goes on previous block to the conditional, diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c index bdcf816bd12..d3f41025b92 100644 --- a/src/freedreno/ir3/ir3_context.c +++ b/src/freedreno/ir3/ir3_context.c @@ -258,7 +258,7 @@ ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr, unsigned flags = dest_flags(arr[0]); collect = ir3_instr_create2(block, OPC_META_FI, 1 + arrsz); - ir3_reg_create(collect, 0, flags); /* dst */ + __ssa_dst(collect)->flags |= flags; for (unsigned i = 0; i < arrsz; i++) { struct ir3_instruction *elem = arr[i]; @@ -292,7 +292,7 @@ ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr, } compile_assert(ctx, dest_flags(elem) == flags); - ir3_reg_create(collect, 0, IR3_REG_SSA | flags)->instr = elem; + __ssa_src(collect, elem, flags); } collect->regs[0]->wrmask = MASK(arrsz); @@ -318,8 +318,8 @@ ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst, for (int i = 0, j = 0; i < n; i++) { struct ir3_instruction *split = ir3_instr_create(block, OPC_META_FO); - ir3_reg_create(split, 0, IR3_REG_SSA | flags); - ir3_reg_create(split, 0, IR3_REG_SSA | flags)->instr = src; + __ssa_dst(split)->flags |= flags; + __ssa_src(split, src, flags); split->fo.off = i + base; if (prev) { @@ -406,6 +406,7 @@ create_addr(struct ir3_block *block, struct ir3_instruction *src, int align) instr = ir3_MOV(block, instr, TYPE_S16); instr->regs[0]->num = regid(REG_A0, 0); + instr->regs[0]->flags &= ~IR3_REG_SSA; instr->regs[0]->flags |= IR3_REG_HALF; instr->regs[1]->flags |= IR3_REG_HALF; @@ -451,6 +452,7 @@ ir3_get_predicate(struct ir3_context *ctx, struct ir3_instruction *src) /* condition always goes in predicate register: */ cond->regs[0]->num = regid(REG_P0, 0); + cond->regs[0]->flags &= ~IR3_REG_SSA; return cond; } @@ -510,7 +512,7 @@ ir3_create_array_load(struct ir3_context *ctx, struct ir3_array *arr, int n, mov->barrier_class = IR3_BARRIER_ARRAY_R; mov->barrier_conflict = IR3_BARRIER_ARRAY_W; - ir3_reg_create(mov, 0, flags); + __ssa_dst(mov)->flags |= flags; src = ir3_reg_create(mov, 0, IR3_REG_ARRAY | COND(address, IR3_REG_RELATIV) | flags); src->instr = arr->last_write; diff --git a/src/freedreno/ir3/ir3_group.c b/src/freedreno/ir3/ir3_group.c index 4ff362b9990..bd7ef2b612e 100644 --- a/src/freedreno/ir3/ir3_group.c +++ b/src/freedreno/ir3/ir3_group.c @@ -61,10 +61,10 @@ static void arr_insert_mov_in(void *arr, int idx, struct ir3_instruction *instr) in = ir3_instr_create(instr->block, OPC_META_INPUT); in->input.sysval = instr->input.sysval; - ir3_reg_create(in, instr->regs[0]->num, 0); + __ssa_dst(in); /* create src reg for meta:in and fixup to now be a mov: */ - ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = in; + __ssa_src(instr, in, 0); instr->opc = OPC_MOV; instr->cat1.src_type = TYPE_F32; instr->cat1.dst_type = TYPE_F32; @@ -209,7 +209,7 @@ pad_and_group_input(struct ir3_instruction **input, unsigned n) block = instr->block; } else if (block) { instr = ir3_NOP(block); - ir3_reg_create(instr, 0, IR3_REG_SSA); /* dummy dst */ + __ssa_dst(instr); /* dummy dst */ input[i] = instr; mask |= (1 << i); } -- 2.30.2