From 5da1d233303c696c208c35a5d9e387785a4f0c7c Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 18 Jun 2022 12:03:46 +0100 Subject: [PATCH] --- openpower/sv.mdwn | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index c8156cbe1..1039abb59 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -131,7 +131,7 @@ Pages being developed and examples * [[sv/svp64]] contains the packet-format *only*, the [[sv/svp64/appendix]] contains explanations and further details * [[sv/svp64_quirks]] things in SVP64 that slightly break the rules -* [[opcode_regs_deduped]] autogenerated table of SVP64 instructions +* [[opcode_regs_deduped]] autogenerated table of SVP64 decoder augmentation * [[sv/vector_comparative_analysis] - a list of Packed SIMD, GPU, and other Scalable Vector ISAs * [[sv/sprs]] SPRs @@ -144,6 +144,8 @@ Pages being developed and examples - For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch behaviour: All/Some Vector CRs - For arithmetic and logical, see [[sv/normal]] + - [[sv/mv.vec]] pack/unpack move to and from vec2/3/4, + actually an RM.EXTRA Mode and a [[sv/remap] mode Core SVP64 instructions: @@ -151,11 +153,23 @@ Core SVP64 instructions: * [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing" * [[sv/svstep]] Key stepping instruction for Vertical-First Mode +*Please note: there are only five instructions in the whole of SV. +Beyond this point are additional **Scalar** instructions related to +specific workloads that have nothing to do with the SV Specification** + +**Additional Instructions for specific purposes (not SVP64)** + +All of these instructions below have nothing to do with SV. +They are all entirely designed as Scalar instructions that, as +Scalar instructions, stand on their own merit. Considerable +lengths have been made to provide justifications for each of these +*Scalar* instructions. + Vector-related: * [[sv/vector_swizzle]] -* [[sv/mv.vec]] pack/unpack move to and from vec2/3/4 -* [[sv/mv.swizzle]] +* [[sv/mv.swizzle]] vec2/3/4 Swizzles (RGBA, XYZW) for 3D and CUDA. + designed as a Scalar instruction. * [[sv/vector_ops]] scalar operations needed for supporting vectors Scalar Instructions: -- 2.30.2